How Alibaba’s UPN512 Redefines AI Scale‑Up Networking with Optical Interconnects

Introduction

At the 2025 Cloud Expo in Hangzhou, the AI Infra Predictable Network forum released the UPN512 Technical Architecture Whitepaper, presenting a comprehensive view of emerging AI infrastructure networking trends.

AI Infrastructure Trends

Rapid growth of AI models has driven exponential increases in compute and memory demands, pushing intelligent clusters from thousands to hundreds of thousands of accelerator cards (xPU). High‑performance networking is essential for parallel data exchange across these massive systems.

Model Evolution: Dense to MoE

Mixture‑of‑Experts (MoE) models replace dense architectures, requiring expert parallelism (EP) that demands ultra‑high bandwidth and ultra‑low latency networks.

From Pre‑training to Train‑and‑Inference Integration

Clusters now handle both offline training and online inference, creating mixed traffic patterns and complex communication requirements.

xPU Scale‑up via High‑Bandwidth Interconnects

Scaling from 8‑card to 384‑card nodes (e.g., NVIDIA GPU Scale‑up, Huawei UB‑NPU) necessitates network designs that support massive bandwidth and low latency.

Challenges of Scale‑up Networks

Current copper‑based interconnects are limited by distance and density, leading to high‑density rack designs that increase complexity, reliability risks, and cost. Optical interconnects are needed for larger scales.

Cost Challenges of Optical Interconnects

Optical solutions are more expensive than copper; however, switch‑based architectures offer better performance at higher cost, while torus interconnects reduce cost but sacrifice performance.

Reliability Challenges

Optical links must handle error correction (FEC, LLR) and fault recovery, with larger systems experiencing higher failure rates, demanding robust fault‑tolerant designs.

Optical Interconnect Overview

Four optical technologies are considered:

FRO (Fully Retimed Optics) : Includes DSP, high cost, latency, and power.

LPO (Linear Pluggable Optics) : DSP‑free, lower cost (~30% cheaper), suitable when SerDes capability is strong.

NPO (Near‑Packaged Optics) : Integrated near the chip, higher bandwidth density, lower cost (~10% cheaper than LPO), easier to standardize.

CPO (Co‑Packaged Optics) : Integrated with the switch chip, highest performance but limited ecosystem.

UPN512 Architecture Overview

UPN (Ultra Performance Network) adopts three key design principles:

High‑radix Ethernet enabling up to 512‑node (future 1K+) single‑layer networks.

LPO/NPO optical interconnects to break distance limits and decouple from dense rack constraints.

Single‑layer switch‑based protocol design to simplify networking and reduce compute overhead.

The architecture delivers "large‑scale, high‑performance, high‑reliability, low‑cost, and scalable" xPU Scale‑up systems.

System Architecture

AI Rack (copper‑based) provides dense 4‑xPU modules but suffers from limited distance, high manufacturing difficulty, power/thermal challenges, and fault impact. UPN512 replaces copper with single‑layer optical interconnects, allowing box‑type devices and standard cabinets.

Optical Interconnect Choices

LPO offers plug‑in modules with 400G‑800G bandwidth, while NPO provides near‑chip integration with 3.2T‑6.4T capacity, higher bandwidth density, and lower cost. Both reduce power (~50%) and latency (~110 ns) compared to FRO.

Cost and Reliability Benefits

LPO reduces cost by ~30% vs. FRO.

NPO further reduces cost by ~10% vs. LPO.

Reliability improves: LPO links approach copper stability; NPO’s short electrical paths increase signal integrity.

Low‑Latency Transmission and Tensor Semantics

UPN512 uses an ETH+ protocol stack with three communication semantics:

Load/Store (memory‑level, ultra‑low latency).

Send/Recv (DMA‑based message passing for large tensors).

Tensor Push/Pull (optimized 1‑100 KB transfers for large‑model workloads).

Tensor semantics provide asynchronous I/O, batch/streaming modes, explicit/implicit acknowledgments, minimal per‑tensor latency, optional compression, and in‑network computing support.

In‑Network Computing

Switches incorporate compute engines supporting INT8/FP16/FP32/BFloat16 and reduction operations (Min/Sum/Max). They accelerate collective communications (AllReduce, AllGather, Dispatch, Combine) by performing reductions inside the network, reducing data movement and CPU/GPU load.

Both symmetric (Broadcast, AllReduce) and asymmetric (Dispatch, Combine) collectives are handled with virtual address registration, PUSH/PULL semantics, and per‑tensor routing.

Conclusion

UPN512 presents a unified solution for AI Scale‑up networking, combining high‑radix Ethernet, cost‑effective LPO/NPO optical interconnects, and in‑network computing to achieve ultra‑high bandwidth, ultra‑low latency, reliability, and scalability for future massive AI models.