Mastering Register and Function‑Pointer Techniques for NAND Flash in Embedded C

Operating Hardware Registers

In embedded C, a hardware register is accessed by defining a macro that maps a fixed physical address to a volatile pointer. The volatile qualifier forces each read/write to occur directly on the hardware, preventing compiler caching.

#define GSTATUS1 (*(volatile unsigned int *)0x560000B0)

A NAND‑Flash controller register block can be represented with a struct whose members correspond to the controller’s 32‑bit registers. The struct is then cast to the controller’s base address.

typedef struct {
    S3C24X0_REG32 NFCONF;
    S3C24X0_REG32 NFCMD;
    S3C24X0_REG32 NFADDR;
    S3C24X0_REG32 NFDATA;
    S3C24X0_REG32 NFSTAT;
    S3C24X0_REG32 NFECC;
} S3C2410_NAND;

static S3C2410_NAND *s3c2410nand = (S3C2410_NAND *)0x4e000000;

/* Byte‑wise access to the status register */
volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFSTAT;

Using Function Pointers

Function pointers store the address of a function and can be invoked like ordinary functions. This mechanism enables callbacks and reduces code duplication.

#include <iostream>

int max(int a, int b) { return (a > b) ? a : b; }

int (*test)(int, int);

int main() {
    test = max;                     // assign function address
    int larger = (*test)(1, 2);     // invoke via pointer
    std::cout << larger << std::endl;
    return 0;
}

NAND‑Flash Driver with Function‑Pointer Table

A structure of function pointers abstracts the NAND‑Flash operations for different SoC families (e.g., S3C2410 and S3C2440). At runtime the driver detects the chip and populates the table with the appropriate implementation.

typedef struct {
    void (*nand_reset)(void);
    void (*wait_idle)(void);
    void (*nand_select_chip)(void);
    void (*nand_deselect_chip)(void);
    void (*write_cmd)(int);
    void (*write_addr)(unsigned int);
    unsigned char (*read_data)(void);
} t_nand_chip;

static t_nand_chip nand_chip;

/* Forward declarations of chip‑specific functions */
static void s3c2410_nand_reset(void);
static void s3c2410_wait_idle(void);
/* ... other S3C2410 prototypes ... */
static void s3c2440_nand_reset(void);
static void s3c2440_wait_idle(void);
/* ... other S3C2440 prototypes ... */

void nand_init(void) {
    #define TACLS   0
    #define TWRPH0  3
    #define TWRPH1  0

    if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002)) {
        /* S3C2410 specific assignments */
        nand_chip.nand_reset        = s3c2410_nand_reset;
        nand_chip.wait_idle         = s3c2410_wait_idle;
        nand_chip.nand_select_chip = s3c2410_nand_select_chip;
        nand_chip.nand_deselect_chip = s3c2410_nand_deselect_chip;
        nand_chip.write_cmd         = s3c2410_write_cmd;
        nand_chip.write_addr        = s3c2410_write_addr;
        nand_chip.read_data         = s3c2410_read_data;
        s3c2410nand->NFCONF = (1<<15)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
    } else {
        /* S3C2440 specific assignments */
        nand_chip.nand_reset        = s3c2440_nand_reset;
        nand_chip.wait_idle         = s3c2440_wait_idle;
        nand_chip.nand_select_chip = s3c2440_nand_select_chip;
        nand_chip.nand_deselect_chip = s3c2440_nand_deselect_chip;
        nand_chip.write_cmd         = s3c2440_write_cmd;
#ifdef LARGER_NAND_PAGE
        nand_chip.write_addr        = s3c2440_write_addr_lp;
#else
        nand_chip.write_addr        = s3c2440_write_addr;
#endif
        nand_chip.read_data         = s3c2440_read_data;
        s3c2440nand->NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);
        s3c2440nand->NFCONT = (1<<4)|(1<<1)|(1<<0);
    }
    nand_reset();   // reset the NAND chip
}

This design makes the driver portable: adding support for a new chip only requires extending the nand_init decision block and providing the corresponding function implementations.

Bit‑Level Register Manipulation

Individual bits of a register are often configured with bitwise operations. The typical pattern is to clear the target bit(s) using a mask and then set the desired value.

#define GPFCON (*(volatile unsigned long *)0x56000050)

/* Clear bit 3 */
GPFCON &= ~(0x1 << 3);

/* Set bit 3 */
GPFCON |=  (0x1 << 3);

These three techniques—macro‑defined volatile registers, function‑pointer tables, and explicit bitwise register control—constitute the core of low‑level embedded programming for NAND‑Flash devices.