Simulating MDIO Communication with GPIO on Linux

Introduction

In some projects the PHY MDIO pins are wired to two free GPIOs on the SoC, making it impossible to use the native GMAC MDIO controller. Linux provides a bit‑bang MDIO implementation that can drive MDIO through GPIO, requiring the mdio-bitbang.c and mdio-gpio.c drivers.

MDIO Basics

MDIO (Management Data Input/Output) is a two‑wire serial interface (MDC clock and MDIO data) defined by IEEE 802.3 for MAC‑PHY management. It operates at up to 2.5 MHz, supports up to 32 PHYs on a shared bus, and follows a master‑slave model where the MAC polls the PHY for status and configuration.

MDIO Frame Structure

Two frame formats exist: Clause 22 for 10/100 Mbps Ethernet and Clause 45 for 1 Gbps and above. Both start with a 32‑bit preamble of logical ‘1’, followed by a start‑of‑frame (01), an operation code (read = 10, write = 01), a 5‑bit PHY address, a 5‑bit register address, a turnaround field, and a 16‑bit data field. The turnaround field determines the direction change for reads; writes keep the MAC driving the line.

Clause 22 Example

向phy：3 寄存器0x00 写入 数据0x4140

The above illustrates writing value 0x4140 to register 0x00 of PHY address 3. The corresponding waveform is shown in the accompanying image.

Clause 45 Overview

Clause 45 adds a device address field and a different opcode layout, used for higher‑speed Ethernet. The article includes the relevant timing diagram.

YT8521 PHY Details

The YT8521S is an Ethernet transceiver compliant with 10BASE‑T, 100BASE‑TX, and 1000BASE‑T. Its MDIO‑related pins are:

14  MDC          Management Data Clock
15  MDIO         Input/Output of Management Data.
    Pull‑up 3.3V/2.5V/1.8V for 3.3V/2.5V/1.8V I/O respectively

Pin‑out diagrams and module block diagrams are provided.

Driver Porting

Source Files

mdio-gpio.c
mdio-bitbang.c

These files implement the GPIO‑controlled MDIO bus. The kernel configuration must enable the following options:

<*>   Bitbanged MDIO buses
<*>   GPIO controlled MDIO bus multiplexers
<*>   MMIO device‑controlled MDIO bus multiplexers

Device‑Tree Configuration

aliases {
    mdio-gpio0 = &mdio0;
};

mdio0: mdio {
    compatible = "virtual,mdio-gpio";
    gpios = <&portc 2 0>, <&portc 3 0>;
    #address-cells = <1>;
    #size-cells = <0>;

    phy0: ethernet-phy@7 {
        reg = <0x7>;
        yt,phy-delay = <0xfc>;
        phy-connection-type = "rgmii-id";
    };
};

&gmac0 {
    status = "okay";
    phy-handle = <&phy0>;
};

The tree creates an independent MDIO device node; when the mdio command is issued, the kernel resolves gmac0 's phy‑handle to this node and invokes the mdio‑gpio driver to talk to the YT8521.

Verification

Boot logs show successful driver probing:

# dmesg | grep MDIO
[    3.257270] libphy: GPIO Bitbanged MDIO: probed
[    3.274202] libphy: Fixed MDIO Bus: probed

Inspecting /sys/class/mdio_bus/ reveals the created gpio‑0 bus and its PHY device entries.

MDIO Command Usage

To set eth0 to 100 Mbps, write 0x2140 to register 0x00 of PHY address 0x3 (Speed_Selection = 01, Autoneg_En disabled):

# mdio eth0 0x00 0x2140
write phy addr: 0x3  reg: 0x0  value : 0x2140

The resulting waveform is displayed in the final image.