Understanding Ethernet MAC, PHY, and MII Interfaces: From Basics to Advanced Variants

Overview

Ethernet’s Media Access Control (MAC) sub‑layer and the Physical Layer (PHY) are linked by the Media Independent Interface (MII). Variants such as GMII, RMII and RGMII provide different data widths and clock rates while preserving compatibility with the IEEE 802.3 standard.

MAC Layer

The MAC implements the data‑link sub‑layer (IEEE 802.3). It receives IP (or other network‑layer) packets from the host bus, fragments them into Ethernet frames (64 – 1518 bytes), inserts source and destination MAC addresses, the type/length field and a 32‑bit CRC. MAC logic can be integrated in a microcontroller or exist as a separate ASIC and works together with a PHY to place bits on the physical medium.

PHY Layer

The PHY implements the physical layer defined by IEEE 802.3. It consists of the PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment), PMD (Physical Medium Dependent) and MDI sub‑layers. The PHY provides the analog front‑end for twisted‑pair or fiber, and exposes status (speed, duplex, link) and control registers to the MAC.

MII Interface

MII is a 4‑bit parallel data bus plus control and clock signals. It uses 16 pins per port:

TXD[3:0] – transmit data driven by the Reconciliation Sublayer (RS), sampled on TX_CLK when TX_EN is high.

TX_EN – transmit enable.

TX_ER – transmit coding error; when asserted with TX_EN the data on TXD is ignored.

TX_CLK – continuous clock from the PHY (2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps).

COL – collision detected (valid only in half‑duplex mode).

RXD[3:0] – receive data from the PHY, sampled on RX_CLK when RX_DV is high.

RX_DV – receive‑data‑valid, indicates that a complete frame is being received.

RX_ER – receive error.

RX_CLK – receive clock, driven by the PHY.

CRS – carrier sense, asserted while a transmission or reception is in progress.

The interface supports 10 Mbps and 100 Mbps operation; the data path is 4 bits wide, giving a maximum throughput of 100 Mbps.

Management Interface (MDIO/SMI)

MDIO (Management Data Input/Output) and MDC (Management Data Clock) form a serial management bus that lets the MAC (STA – Station Management Entity) read and write PHY registers.

Clause 22: up to 32 PHY devices, each with 32 registers.

Clause 45: up to 32 PHY devices, each with up to 64 K registers.

Timing requirements:

STA‑driven MDIO must have ≥10 ns setup and hold relative to the rising edge of MDC.

PHY‑driven MDIO output delay (Tco) may be 0 ns – 300 ns.

MDC is typically ≤2.5 MHz, but some PHYs (e.g., Marvell 88E1512) support up to 12 MHz.

Pull‑up ≈1.5 kΩ and pull‑down ≈2 kΩ on MDIO are recommended, though some PHYs only require the pull‑up.

Derived Interfaces

RMII – reduces the data pins to two (TXD, RXD) and uses a 50 MHz clock for 100 Mbps (5 MHz for 10 Mbps). Pin count is halved compared with MII.

GMII – 8‑bit data bus with a 125 MHz clock, supporting 1 Gbps while remaining backward compatible with 10/100 Mbps modes.

RGMII – 4‑bit data bus with double‑data‑rate clocking (data on both rising and falling edges) to achieve 1 Gbps using a 125 MHz clock. TX_CTL combines TX_EN/TX_ER; RX_CTL combines RX_DV/RX_ER.

RGMII Timing Details

At 1 Gbps the TXC/RXC clock runs at 125 MHz. TXD[3:0] are transmitted on the rising edge, TXD[7:4] on the falling edge; TX_CTL carries TX_EN on the rising edge and TX_ER on the falling edge. The receive side mirrors this behavior, allowing full‑rate gigabit transmission with only four data lines.

MDIO Frame Formats

Clause 22 (32‑bit) frame: ST | OP | PHYAD | REGAD | TA | DATA where ST=01, OP=read/write, PHYAD=5 bits, REGAD=5 bits, TA=2 bits (turn‑around), DATA=16 bits.

Clause 45 (64‑bit) frame adds a device type field and an extended address field, enabling access to the larger register space of modern PHYs.

Practical Design Considerations

Pin count: a full‑MII port needs 14 signals; an 8‑port switch therefore requires 112 pins, making MII impractical for high‑port‑count designs.

Isolation transformer between PHY and RJ‑45 provides DC blocking, common‑mode rejection and protection against surges.

EEPROM (commonly 93C46) stores the MAC address, PHY address on the MDIO bus, and optional boot‑ROM configuration.

Power‑management circuitry must keep the PHY and a subset of MAC logic powered from standby voltage to support Wake‑on‑LAN while minimizing standby current.

Typical Ethernet Card Block Diagram

Key components are the PCI/PCIe interface, MAC controller, PHY chip (or integrated MAC+PHY), isolation transformer, EEPROM, optional boot ROM, power‑conversion circuitry, and optional WOL connector.