Understanding Memory Speed, Core Frequency, and Latency Across DDR Generations

Since the introduction of DDR memory in 2001, the industry has progressed through DDR, DDR2, DDR3, and DDR4 (with DDR5 now emerging), while the nominal memory frequency has risen from 266 MHz to 3200 MHz. In operating systems this frequency is called Speed or effective frequency, and a higher value means greater memory I/O throughput.

The most fundamental frequency of a memory module is the core frequency, the actual oscillation rate of the memory circuitry, which largely determines I/O latency. Over the past 18 years the core frequency has seen little improvement, remaining roughly between 133 MHz and 200 MHz due to physical material limits.

On Linux you can view the Speed of each memory device with a command such as:

# dmidecode | grep -P -A16 "Memory Device"
Memory Device
Array Handle: 0x0009
Error Information Handle: Not Provided
Total Width: 72 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: DIMM02
Bank Locator: BANK02
Type: Other
Type Detail: Unknown
Speed: 1067 MHz
Manufacturer: Micron
Serial Number: 65ED91DC
Asset Tag: Unknown
Part Number: 36KSF1G72PZ-1G4M1
......

The output shows two key values for developers: Speed (e.g., 1067 MHz) and Data Width (e.g., 64 bits). Multiplying these yields the data bandwidth. Historical Speed and bandwidth data for various DDR generations are illustrated in the following chart:

The "core frequency" is the true operating frequency of the memory circuit and forms the basis for all other derived frequencies. While the advertised Speed (or effective frequency) is amplified from the core frequency using techniques such as prefetch and bank‑group designs, the core frequency itself has stagnated.

Figures below compare core frequencies and the technical tricks used in each DDR generation:

From the SDR era to modern DDR4, core frequency has remained roughly 133–200 MHz, while manufacturers have increased the effective Speed by:

SDR era: Raising the core clock directly.

DDR era: Using both rising and falling edges to double the effective frequency.

DDR2 era: Prefetch increased to 4, yielding four‑times the core frequency.

DDR3 era: Prefetch increased to 8, yielding eight‑times the core frequency.

DDR4 era: Prefetch still 8, but introduction of Bank Group architecture allows up to sixteen‑times the core frequency.

Memory also has an IO frequency (or clock frequency) roughly equal to Speed/2; it must match the CPU’s external clock to operate correctly. For example, a DDR3 module with a 133 MHz core frequency and a 533 MHz CPU external clock yields an IO frequency of 533 MHz and an effective Speed of 1066 MHz.

Latency parameters (CL‑tRCD‑tRP‑tRAS) are not easily visible in Linux, and many sellers omit them. The first three values (CL‑tRCD‑tRP) are critical; for example, DDR3‑1066 typically has CL‑tRCD‑tRP of 7‑7‑7, while a popular DDR4‑2400 module may list 17‑17‑17.

Although newer memory appears faster, the latency cycle (calculated as latency time divided by Speed) can seem larger because Speed is an amplified metric, not the true operating frequency. Since core frequency has not improved, the actual latency time remains roughly constant.

In summary, the real working frequency of memory is the core frequency; Speed and IO frequency are derived by technological amplification, and the apparent increase in latency cycles is a side effect of using Speed as the reference metric.