Unlock Faster, Safer Embedded Systems with Asymmetric AMP Dual‑OS Architecture

What Is Asymmetric AMP Dual‑System?

Asymmetric multiprocessing (AMP) allows different CPU cores to run independent operating systems or bare‑metal applications, such as Linux on one core and an RTOS or bare‑metal code on another. A designated master core controls the whole system while the slave cores operate autonomously, each with its own memory and optional inter‑core communication.

Benefits for Industrial Applications

Stronger real‑time performance : Fixed cores handle real‑time tasks, enabling complex industrial control functions without sacrificing deterministic response.

Higher system stability : Cores are isolated with separate memory, reducing cross‑core interference and lowering crash probability.

Lower hardware cost : A single shared hardware platform runs multiple OSes, eliminating the need for duplicate CPU/ROM/RAM/PMIC circuits.

Development Case on the RK3568J SOM

The Chuanglong Technology RK3568J industrial SOM (SOM‑TL3568) provides a ready‑made platform for asymmetric AMP development. All components—CPU, ROM, RAM, power, crystal, connectors—are domestically sourced, achieving 100% local component rate.

Step‑by‑Step UART Echo Demo

Copy the amp.img file supplied with the case to the board’s file system.

Flash the image to the Linux boot partition: dd if=amp.img of=/dev/mmcblk1p8 conv=fsync Synchronize and reboot the board:

sync

reboot

Before the Linux kernel boots, enter U‑Boot command mode (press space during the countdown) and disable the default UART nodes to free the RS485 UART7 port for the demo:

fdt set /serial@fdd50000 status "disable"

fdt set /serial@fe6b0000 status "disable"

Boot the system; the amp.img loads, launching Linux on three cores (CPU0‑CPU2) and a Baremetal/RT‑Thread RTOS on CPU3. The RS485 UART7 port echoes any characters entered, demonstrating inter‑core communication.

The following images illustrate the hardware board, U‑Boot prompt, and terminal output for both the Baremetal and RT‑Thread implementations.