Why Chinese CPUs Require Full Memory Population: Chiplet NUMA vs Intel's Monolithic Design

Surface Difference: Chip Architecture Dictates NUMA Granularity

Operations and localization engineers often encounter a puzzling requirement: domestic server vendors mandate that memory slots be filled in pairs across all channels. Missing even one set of DIMMs can degrade database and virtualization performance by 30–50%. In contrast, Intel Xeon servers run fine with 2 or 4 DIMMs arbitrarily placed; bandwidth and latency degradation is barely noticeable.

Both platforms use NUMA (Non-Uniform Memory Access), yet the memory‑population sensitivity differs drastically. The root cause lies in four layers: chip architecture, die‑to‑die interconnect, firmware/kernel scheduling, and ecosystem maturity.

1. Intel Xeon: Near‑UMA Within a Socket, Coarse NUMA Granularity

Traditional Intel Xeon processors employ a monolithic die + ring bus design. All compute cores, L3 cache, and memory controllers sit on a single ring bus, so the entire processor counts as one NUMA node . Only in multi‑socket (2‑socket, 4‑socket) systems does each socket become a separate NUMA node, yielding at most 4 nodes total — a very coarse granularity.

Memory channels are global resources of the socket. Populating only half the channels merely reduces total bandwidth slightly. The BIOS enables memory interleaving by default, automatically striping data across channels to smooth imbalances. Local vs. remote (cross‑socket) memory latency differs by only 1.2–1.5×, so occasional remote accesses incur minimal penalty and everyday workloads are unaffected.

2. Domestic CPUs: Chiplet‑Based, Fine‑Grained NUMA Topology

Due to yield limitations of domestic DUV lithography, mainstream Chinese server CPUs — whether Hygon (x86), Kunpeng, or Phytium (ARM) — adopt multi‑chiplet (Chiplet) packaging:

Hygon: Inherits AMD’s CCD modular design. A single CPU is split into multiple compute chiplets, creating 4–8 micro NUMA units , each bound to dedicated memory channels.

Kunpeng / Phytium: Use multi‑die mesh interconnects. A single CPU natively partitions into 4 compute blocks , each owning its own memory channels, resulting in a naturally fragmented NUMA topology.

The critical pain point emerges when memory channels are not uniformly populated: some NUMA nodes have no local memory . Cores must then traverse the die‑to‑die interconnect to fetch data from remote nodes. Local vs. remote latency gap widens to over 2× , and under concurrency the interconnect congests, drastically cutting bandwidth. Database reads/writes, VM scheduling, and middleware forwarding all exhibit visible stalls.

Core Bottleneck: Die‑to‑Die Interconnect Bus

The NUMA experience ceiling is set by the cross‑node interconnect:

Intel UPI (Ultra Path Interconnect): Over a decade of iteration provides ample bandwidth headroom, mature congestion control, low cross‑socket latency, and a polished cache‑coherency protocol. Sparse remote accesses cause no system jitter.

Domestic Interconnects (Infinity Fabric / HCCS): Later start means lower bandwidth ceilings, higher latency, and weaker congestion resistance. As node count grows, cross‑node access penalties accumulate. Bursts of scattered remote memory requests easily saturate the bus, amplifying performance loss. Without sufficient hardware headroom to absorb imbalance‑induced traffic, the safest mitigation is to guarantee every micro NUMA node has its own local memory.

3. Firmware & Linux Kernel Scheduling: Decades of Ecosystem Gap

Intel’s Deep Kernel Integration: Intel has contributed to the Linux kernel for decades, optimizing for coarse‑grained NUMA: automatic background memory balancing, latency‑aware thread scheduling, remote‑access prediction. Even with uneven memory layout, the OS silently migrates pages and adjusts thread affinity, dampening NUMA side‑effects.

Domestic CPU Adaptation Still Maturing: Commercial deployment cycles are shorter. Kernel‑specific optimizations cover less ground: the built‑in NUMA auto‑balancing is less effective, and enabling page migration can introduce workload jitter. Most scenarios require manual core pinning and memory‑node partitioning, raising operational complexity. To reduce misconfiguration risk and ensure delivery stability, vendors enforce a hard rule: fill all channels evenly , eliminating fine‑grained NUMA hazards at the source.

Moreover, commercial software (MySQL, Oracle, virtualization platforms) has long been tuned against Intel’s NUMA topology. Migrating to domestic fine‑grained NUMA environments with imbalanced memory layouts readily triggers performance bugs, making full memory population the de‑facto safe standard for localization projects.

4. Clarifying a Misconception: Intel Also Recommends Full Population for Extreme Bandwidth

In HPC, in‑memory databases, and ultra‑high‑concurrency caching — scenarios demanding maximum bandwidth — Intel likewise advises populating all channels to saturate total memory throughput. The difference is that half‑population on Intel is tolerable for general workloads.

AMD EPYC shares the same chiplet heritage as Hygon, so it also imposes far stricter memory‑uniformity requirements than Intel. This is a common trait of high‑core‑count x86 chiplet designs.

Conclusion

The mandatory full‑channel memory rule for domestic CPUs is not a design flaw but a pragmatic compromise driven by chiplet fragmentation + limited die‑to‑die interconnect bandwidth/latency + insufficient software ecosystem polish . Intel’s monolithic architecture, mature interconnect, and decades of system‑software co‑optimization grant it a much larger error margin.

As domestic silicon iterates, interconnect technology advances, and Linux kernel adaptations continue, the memory‑population tolerance of Chinese server CPUs will steadily improve. For now, however, adhering to the principle of uniform full‑channel memory population remains the primary guideline for ensuring stable, high‑performance operation in localization deployments.