Why Nvidia’s Blackwell GPU Beats AMD RDNA4: Deep Dive into GB202 Architecture

Nvidia has long pursued giant GPUs, and its latest Blackwell architecture continues this trend. The flagship GB202 chip occupies 750 mm² and contains 92.2 billion transistors, featuring 192 streaming multiprocessors (SMs) and a massive memory subsystem.

The RTX PRO 6000 Blackwell uses the largest GB202 configuration, sharing the chip with the RTX 5090, which disables additional SMs.

High‑level comparisons show Blackwell versus AMD’s RDNA4 series, using the RX 9070 as a benchmark. The RX 9070 disables four of its 32 WGPs, providing a basis for performance data.

GPU work is launched by dedicated hardware threads across cores, unlike CPU software scheduling. SMs act as the GPU’s core equivalents, grouped into graphics processing clusters (GPCs) that include rasterizers and work‑distribution hardware.

GB202’s SM‑to‑GPC ratio is 1:16, compared to Ada Loveland’s AD102 ratio of 1:12, allowing Nvidia to increase SM count cost‑effectively without adding more GPC hardware. However, short‑wave scheduling may limit throughput because GPC‑to‑SM work distribution, not SM execution speed, becomes the bottleneck.

AMD’s RDNA4 uses a 1:8 SE:WGP ratio, with each rasterizer feeding eight WGPs. WGPs are AMD’s closest analogue to Nvidia’s SMs, sharing the same nominal vector lane count. RDNA4’s design is not unique; extending GPU cores via work‑distribution hardware is common. AMD’s previous GPUs (RX 6900XT, Fury X, Vega 64) had varying SE:WGP or SE:CU ratios, influencing performance.

Blackwell’s RTX PRO 6000 does not expand work‑distribution hardware but improves scheduling. Earlier Nvidia GPUs required sub‑channel switches and idle waits when mixing workload types; Blackwell removes sub‑channel switches, allowing more efficient shader array filling.

SM front‑end fetches shader instructions and delivers them to execution units. Blackwell uses fixed‑length 128‑bit (16‑byte) instructions and a two‑level instruction cache inherited from Volta/Turing. Each SM has four private L0 caches and a shared L1 cache.

The long 16‑byte instructions increase bandwidth demand; the L0+L1 cache hierarchy handles this while keeping power low. L1i is estimated at 128 KB, supporting ~8 KB of instructions, a significant increase over previous generations.

SM‑level changes include a 32 KB L0i cache (up from Turing’s 16 KB) and a shared 128 KB L1/Shared memory block, which can be partitioned between L1 cache and shared memory. Bandwidth limits may appear when multiple waves exceed L1i capacity.

AMD’s RDNA4 uses variable‑length 4‑12‑byte instructions, reducing cache pressure. It shares a 32 KB instruction cache across WGPs, with a 16 KB scalar cache per WGP. RDNA4’s L1i can sustain 32 bytes per SIMD per cycle, handling its compact instructions efficiently.

SMs can track up to 12 waves (vs. RDNA4’s 16 per SIMD). Register file size (64 KB per SM partition) limits active wave usage; AMD’s WGPs have larger vector register files (192 KB), allowing more registers per wave.

Blackwell’s FP32 and INT32 pipelines are reorganized into a single 32‑bit wide execution pipeline, enabling higher throughput for homogeneous operations compared to AMD’s RDNA and Nvidia’s Pascal.

AMD’s RDNA4 WGPs feature dual‑issue VOPD instructions and up to 64 FP32 ops per cycle per partition, plus eight special function units (SFUs) versus Nvidia’s four.

Blackwell’s massive SM count masks per‑partition differences; even with RX 9070’s dual‑issue capability, its 28 WGPs cannot match the 188 SMs of Nvidia.

Atomic operations are handled by dedicated ALUs near the memory hierarchy. Nvidia provides 16 INT32 atomic ALUs per SM, while AMD offers 32 per WGP.

Both GPUs show similar global‑memory atomic add throughput, but Nvidia’s L2 storage appears to have fewer atomic units.

Latency for atomic compare‑and‑swap is comparable, with AMD slightly faster. Ray‑tracing hardware in Blackwell doubles triangle‑intersection rates per SM and supports opacity micro‑maps.

Blackwell’s memory subsystem includes a 128 KB SM‑wide block split into L1 cache and shared memory, similar to Ada Loveland. AMD’s equivalent is LDS, while Intel calls it SLM. L1/Shared memory partitioning does not affect L1 latency.

AMD’s WGP memory subsystem comprises a 128 KB LDS split into two 64 KB banks, a 32 KB L0 vector cache per SIMD, and a 16 KB scalar cache, totaling 208 KB per WGP.

Blackwell’s L2 cache is larger (≈8.7 TB/s bandwidth) than RDNA4’s (≈8.4 TB/s), but its latency (~130 ns) is higher than Ada Loveland’s 107 ns. Vulkan tests show RTX 5070’s L2 latency exceeds that of RTX 4090 despite fewer SMs.

VRAM latency for RTX PRO 6000 is ~329 ns (L2 hit ~200 ns), while RDNA4 achieves lower vector (254 ns) and scalar (229 ns) latencies. Blackwell’s GDDR7 and 512‑bit bus maintain a lead in memory bandwidth.

FluidX3D benchmark demonstrates Nvidia’s RTX PRO 6000 vastly outperforms AMD’s RX 9070 in compute and memory bandwidth, regardless of FP16 conversion.

Looking ahead, GPU competition will intensify with Intel’s upcoming GPUs, while AMD’s MI300 dominates data‑center workloads. In the high‑end consumer market, Nvidia’s Blackwell remains unmatched due to its sheer SM count, larger L2 cache, and superior memory bandwidth, despite challenges in L2 performance and power consumption.

Source: Compiled from hipsandcheese; reposted by Semiconductor Industry Watch.