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Deepin Linux
Deepin Linux
Dec 2, 2025 · Fundamentals

Why CPU Cache Misses Slow Down Your Linux System—and How to Fix Them

CPU caches bridge the speed gap between processors and memory, but cache misses can dramatically degrade performance, especially under high concurrency or big‑data workloads; this article explains cache architecture, common miss causes, diagnostic tools like perf and cachestat, and practical optimization techniques for Linux systems.

CPU cacheLinux performanceMESI Protocol
0 likes · 44 min read
Why CPU Cache Misses Slow Down Your Linux System—and How to Fix Them
Deepin Linux
Deepin Linux
Jul 21, 2025 · Fundamentals

Unlocking CPU Speed: How Cache Bridges the Gap Between Processor and Memory

This article explains why modern CPUs need cache memory, describes the hierarchy of L1‑L3 caches, the principles of locality, write policies, multi‑core coherence mechanisms such as bus snooping and the MESI protocol, and offers practical code‑level optimizations to improve cache performance.

CPUCacheMESI Protocol
0 likes · 31 min read
Unlocking CPU Speed: How Cache Bridges the Gap Between Processor and Memory
Linux Kernel Journey
Linux Kernel Journey
Feb 5, 2025 · Fundamentals

Boost Code Performance by Leveraging CPU Cache Principles

This article explains how CPU caches bridge the speed gap between the processor and main memory, describes cache hierarchy, locality principles, write policies, coherence protocols, and provides concrete C code examples and practical tips such as data alignment and loop restructuring to improve cache hit rates and overall program speed.

CPU cacheMESI ProtocolMemory Hierarchy
0 likes · 30 min read
Boost Code Performance by Leveraging CPU Cache Principles
Deepin Linux
Deepin Linux
Feb 4, 2025 · Fundamentals

Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques

This article explains the fundamental role of CPU cache in bridging the speed gap between processors and memory, covering cache hierarchy, locality principles, write policies, coherence protocols, and practical code optimizations such as data alignment and loop restructuring to improve performance.

CPU cacheData AlignmentMESI Protocol
0 likes · 31 min read
Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques
Tencent Cloud Developer
Tencent Cloud Developer
Nov 1, 2022 · Fundamentals

Understanding CPU Cache, Memory Hierarchy, and Virtual Memory

The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.

CPU cacheMESI ProtocolMemory Hierarchy
0 likes · 16 min read
Understanding CPU Cache, Memory Hierarchy, and Virtual Memory
IT Services Circle
IT Services Circle
Mar 9, 2022 · Fundamentals

A Curated Collection of Visualization Websites for Algorithms, Data Structures, MESI Protocol, and TCP Mechanisms

This article compiles a variety of online visualization tools—including algorithm and data‑structure animators, a MESI cache‑coherency simulator, and interactive TCP sliding‑window and flow‑control demos—to help learners intuitively understand core computer‑science concepts through animated models and hands‑on experimentation.

Data StructuresMESI ProtocolTCP
0 likes · 11 min read
A Curated Collection of Visualization Websites for Algorithms, Data Structures, MESI Protocol, and TCP Mechanisms
vivo Internet Technology
vivo Internet Technology
Jan 6, 2021 · Fundamentals

Deep Dive into Java Volatile Keyword: CPU Cache, MESI Protocol, and JMM

The article thoroughly explains how CPU caches and the MESI coherence protocol interact with Java’s Memory Model, detailing the volatile keyword’s role in ensuring visibility and preventing instruction reordering, and illustrates these concepts with examples such as visibility problems and double‑checked locking.

CPU cacheInstruction ReorderingJMM
0 likes · 22 min read
Deep Dive into Java Volatile Keyword: CPU Cache, MESI Protocol, and JMM
Qunar Tech Salon
Qunar Tech Salon
Mar 31, 2015 · Fundamentals

Understanding CPU Caches, Coherency Protocols, and Memory Models

This article provides a concise introduction to CPU cache architecture, explains read/write policies, describes cache coherency protocols such as MESI and its variants, and discusses how different memory models affect multi‑core consistency and performance.

CPU cacheCache CoherencyMESI Protocol
0 likes · 19 min read
Understanding CPU Caches, Coherency Protocols, and Memory Models