AI Super Nodes: China's 2026 Compute Framework & NVIDIA Vera Rubin Deep Dive

Analyst Report Overview

Analyst Liu Xi released the Computer Super Node OEM Series Report — Super Node: Reconstructing the Intelligent Computing Base, Domestic AI Acceleration Breakthrough . The content centers on super node compute architecture, dissecting large model training and inference underlying bottlenecks, overseas benchmark Vera Rubin full-stack technology, domestic industry progress, market space, and investment opportunities.

I. Underlying Drivers of Super Node Emergence: Multi-Faceted Bottlenecks in Large Model Training and Inference

1. Training-Side Bottlenecks

Mixture-of-Experts (MoE) model expert parallelism (EP) generates high-frequency AlltoAll sparse communication with unpredictable traffic, heavily occupying GPU compute resources. Tensor parallelism (TP) similarly imposes stringent requirements on intra-node interconnect bandwidth and latency. The division between Scale-Up (intra-cabinet tight coupling) and Scale-Out (cross-cluster loose coupling) sees TP/EP converging within the super node's high-bandwidth domain, while pipeline parallelism (PP) and data parallelism (DP) are delegated to external cluster networks.

2. Inference-Side Bottlenecks

Inference splits into Prefill (compute-bound) and Decode (memory-bandwidth-bound). The Decode stage's KV Cache expands with context length, exhibiting large capacity, small-packet high-frequency, latency-sensitive, high-concurrency characteristics. This easily causes memory fragmentation and OOM (out-of-memory) errors. Traditional server clusters suffer low compute utilization, making super nodes a rigid necessity.

3. Core Super Node Optimization Means (Multi-Layer Collaboration)

High-Bandwidth Inter-Chip Interconnect: Evolving across bus, proprietary interconnect, and open Ethernet routes. Scale-Up targets hundred-nanosecond to sub-microsecond latency. NVLink6 per-GPU bidirectional bandwidth far exceeds PCIe.

Unified Memory Addressing: Divided into address layer, access layer, and management layer, enabling HBM/DDR/CXL memory pooling for transparent multi-chip memory access.

Network Topology Optimization: Reducing network diameter, increasing bisection bandwidth, cutting communication hops, building non-blocking networks.

Software Stack Scheduling Optimization: Achieving compute-communication overlap, reducing communication occupancy of SM (Streaming Multiprocessor) units, significantly boosting MFU (Model FLOPs Utilization) and lowering per- Token cost.

II. Overseas Benchmark: NVIDIA Vera Rubin NVL72 Full-Stack Super Node Platform

The platform targets training, inference, storage, and scheduling across all AI scenarios, composed of 7 chips + 5 rack types , representing the overseas super node technology paradigm.

1. Core Hardware & Performance

Rubin GPU: Inference compute improved 5× over Blackwell.

Groq3 LPU (Language Processing Unit): Decouples Attention (GPU) and FFN (LPU) computation. The two collaborate to achieve up to 35× inference performance uplift .

2. Network Technology Evolution

Equipped with NVLink6 switch ASICs, integrating SHARP (Scalable Hierarchical Aggregation and Reduction Protocol) in-network computing to offload collective communication overhead and reduce GPU synchronization pressure.

Network cabling evolves from copper to CPO (Co-Packaged Optics) silicon photonics. Rubin phase uses intra-cabinet copper, inter-cabinet gradually introducing CPO; subsequent Feynman series moves toward full CPO.

Simultaneous volume production of Quantum IB and Spectrum series Ethernet CPO switches.

3. Dedicated Rack Division of Labor

Vera CPU Rack: Targets Agent intelligent agents and massive reinforcement-learning sandbox scenarios. CPU/GPU ratio evolves from traditional 1:8 to 1:1, dramatically improving serial task handling.

BlueField-4 STX Storage Rack: Loads CMX Context Memory Platform, constructing G1-G4 multi-tier KV Cache storage hierarchy to solve long-context inference KV Cache expansion challenges.

Groq3 LPX Rack: Packs large numbers of LPU s to handle FFN feed-forward network computation, achieving high-throughput + low-latency inference balance. Oberon/Kyber next-gen racks support backward compatibility; NVLink-C2C enables CPU-GPU cache-coherent memory access. Full-cabinet high integration increases component count significantly, raising system engineering complexity.

III. Domestic Super Nodes: 2026 as the First Year of Large-Scale Commercial Deployment

1. Multiple Technical Routes in Parallel, Multiple Vendors Launch Turnkey Solutions

Domestic inter-chip interconnect protocols flourish: Huawei UB Lingqu, Hygon Hyswitch, Moore Threads MetaXLink, Alibaba ALink, ByteDance EthLink, Tencent ETHX — iterating along two main routes: private bus and open Ethernet.

Huawei Atlas950 SuperPoD: UB-Mesh topology, maximum 8,192 GPUs fully interconnected, zero-cable interconnect, full liquid cooling. Next-gen Atlas960 SuperPoD targets 15,488 GPUs.

Sugon scaleX640: Single cabinet 640 GPUs, immersion phase-change liquid cooling. Domestic 100k-GPU all-domestic AI cluster already deployed.

Alibaba Panjiu 128 / Lingjun Zhenwu M890 Super Node: Open architecture, supports multiple AI chip types, scalable to million-GPU clusters.

Baidu Tianchi 256-GPU Super Node (Kunlun Xin P800): Already on market, compatible with mainstream domestic large models, orders sufficient.

2. Super Node Market Sizing

2025–2028 domestic super node market size CAGR reaches 341% ; assuming super node penetration continues rising, 2028 market scale expected to exceed 1.1 trillion RMB .

Super nodes are not mere hardware stacking; they fuse high-speed interconnect, liquid cooling, whole-machine structure, power supply, and system tuning — complexity far exceeding traditional servers. OEM vendor value upgrades from simple assembly to system customization, deep integration, and software-hardware co-optimization services .

For the complete report (analyst Liu Xi) and deeper AI super node analysis, refer to AI Super Node Fundamentals Full Analysis (2nd Edition) and Overview of 31 Domestic AI Super Node Solutions .