Sharing project experiences, insights into cutting-edge architectures, focusing on cloud computing, microservices, big data, hyper-convergence, storage, data protection, artificial intelligence, industry practices and solutions.
Google's eighth-generation TPU introduces two specialized chips: TPU 8t with 3D Torus, 9,600-chip pods, 2PB shared HBM, and SparseCore for massive pre-training, and TPU 8i with Boardfly topology, 1,152-chip pods, CAE, and high HBM bandwidth for low-latency Agentic AI inference.
Huawei's Kirin 9050 Pro implements the new Tao Law, replacing geometric scaling with logic folding to achieve a 55% transistor density increase on the same process node, while cutting NPU power 66%, GPU 58%, and CPU core power 41% by using saved timing margin to lower voltage instead of raising frequency.
This article details Huawei's xDeepServe system for deploying massive Mixture-of-Experts models on the CloudMatrix384 supernode, covering the XCCL communication library, FlowServe decentralized serving engine, Transformerless execution architecture with prefill-decode and MoE-Attention decoupling, and hierarchical fault tolerance, achieving 2400 tokens/s per chip at 50ms TPOT.
Huawei's CloudMatrix384 integrates 384 Ascend 910 NPUs with a unified bus network and decoupled PDC service architecture to achieve 4.45 tokens/s/TFLOPS prefill efficiency on DeepSeek-R1 671B, outperforming H100 baselines through fused MoE communication, INT8 quantization, and heterogeneous pipelining.
This article analyzes seven emerging Scale-Up interconnect technologies—UALink, SUE, ESUN, EthLink, ETH+, ETH-X, and CLink—that aim to replace proprietary NVLink for connecting hundreds of XPUs in AI supernodes, detailing their protocol stacks, header optimizations, and industry backing.
The article analyzes the definition, technical traits, and three classifications of supernodes (SuperNode, SuperPoD, SuperCluster), explains how they boost large‑model training and inference efficiency, and examines the evolution of domestic supernode architectures, interconnects, and ecosystem design.
The GEI China Unicorn Enterprise Research Report 2026 shows that China’s unicorns reached a total valuation of over $1.4 trillion in 2025, with more than 80 % in hard‑tech fields and Beijing’s four semiconductor unicorns—Qingwei Intelligent, Kunlun Chip, SMIC Beijing and Yiswei Computing—accounting for over 1300 billion RMB and leading the industry’s shift from internet to advanced chip technologies.
China’s National Intellectual Property Administration awarded HaiGuang Information’s patent on a virtual trusted environment loading and execution method the Gold Prize, highlighting the company’s 2026 R&D spend of 2.652 billion yuan, its 1,388 active patents, and the security features that raise industry entry barriers and drive commercial adoption across cloud, finance, and industrial sectors.
AMD’s upcoming Zen 6 family may introduce a low‑power Zen 6 LP core built by stitching proven Zen 5, Zen 4, and Zen 3 modules—retaining the full Zen 6 ISA while shrinking cache and FPU—to boost thin‑laptop and handheld battery life, though details remain unconfirmed.
The article examines how AI models expose storage bottlenecks, introduces High Bandwidth Flash (HBF) as a 3D NAND‑based, HBM‑like stacked memory that combines subarray parallelism and a dedicated logic die, evaluates its technical principles, industry positioning, benchmark results showing 2.69× performance‑per‑watt gains, supply‑chain landscape, emerging standards, and the challenges that must be solved before commercial deployment.
