Comprehensive Overview of Server Architecture, Classification, and Key Technologies

Servers are familiar to anyone in IT, yet many details of server technology remain unclear; this article aims to give a thorough introduction to server fundamentals.

Servers are broadly divided into non‑x86 (including mainframes, minicomputers, and UNIX servers using RISC or EPIC processors such as IBM Power, PowerPC, SPARC, and Intel Itanium) and x86 servers (CISC‑based machines that typically run Intel‑compatible CPUs and Windows operating systems).

Classification can be based on instruction set architecture (CISC, RISC, EPIC), physical form factor (tower, rack, blade, high‑density), and measurement units such as rack unit (U), capacity units for memory and storage, and data‑rate units (bit/s, B/s).

Port auto‑negotiation is an Ethernet process where connected devices exchange capabilities (10/100/1000 BASE‑T) and select the highest common speed, duplex, and flow‑control mode as defined by IEEE 802.3.

Key server software components include BIOS (basic firmware for power‑on self‑test and boot), UEFI (next‑generation firmware), CMOS (RAM for BIOS settings), BMC (baseboard management controller for monitoring), and the operating system (32‑bit vs 64‑bit, with 64‑bit supporting larger memory).

Relevant standards are ATCA (Advanced Telecom Computing Architecture), OSCA (Huawei’s ATCA‑based platform), and OSTA (Open Standards Telecom Architecture), which define modular, scalable hardware specifications.

The logical structure of a server mirrors a typical computer: CPU, memory, storage, system bus, and additional reliability, stability, and manageability features. CPU cache hierarchy (L1 instruction and data cache, L2 cache, optional L3 cache) bridges the speed gap between the processor and main memory.

Memory (RAM) differs from storage (disk); memory provides fast, volatile workspace, while storage holds persistent data. Memory frequency (MHz) indicates its speed, with higher frequencies generally yielding better performance.

System boot methods include cold start, warm start, and reset start, each varying in the extent of power‑on self‑test and initialization.

Motherboard chipsets consist of north‑bridge (CPU, memory, AGP) and south‑bridge (I/O, IDE, PCI, network) components, each handling different data pathways.

Networking concepts covered are switching (layer‑2 forwarding) versus routing (layer‑3 forwarding), with device types such as access, aggregation, and core switches, and the distinction between stacking (equal‑level logical device) and cascading (hierarchical connections).

Floating‑point precision is explained (half‑precision 16‑bit, single‑precision 32‑bit, double‑precision 64‑bit) and its relevance to scientific computing.

Time synchronization in NTP can be performed via step adjustments (large offset corrected instantly) or slew adjustments (small offset corrected gradually by altering the clock rate).

FC SAN zoning controls access between devices on a Fibre Channel switch, with hard and soft zones based on port IDs or WWNs, and zone sets managing multiple zones.

TPC benchmarks (TPC‑C, TPC‑D, upcoming TPC‑E) provide standardized performance and price metrics for transaction processing and decision‑support workloads.

CPU affinity binds virtual CPUs or processes to specific physical cores to improve cache utilization and scheduling efficiency, though it does not solve load‑balancing issues.

SNMP (versions 1/2c/3) is described as a network management protocol with three main components: the network management system (NMS), managed devices, and agents that expose management information bases (MIBs).

The article concludes with a promotional note offering a 190‑page e‑book titled “Data Center Server Knowledge Complete Guide,” which compiles 18 chapters covering processor families, software stacks, bus architectures, BIOS/UEFI, security, and more, available via a link to the original source.