DDR Memory Principles Explained: From SDRAM to DDR5 Architecture

Memory Classification and DDR Basics

Memory is primarily divided into ROM (Read-Only Memory) and RAM (Random Access Memory). ROM stores pre-written data that persists after power loss. RAM exchanges data directly with the CPU, allows read/write operations, but loses data when powered off. DDR SDRAM (Double Data Rate Synchronous Dynamic RAM) evolved from SDRAM by transmitting data on both rising and falling clock edges, doubling data transfer speed without increasing clock frequency. DDR has evolved through DDR1 to DDR5, with DDR5 now reaching 3200-6400 MT/s data rates.

Core DDR Technical Concepts

Double-edge transfer and prefetch are DDR's core technologies. DDR reads data on both clock edges, achieving twice the speed of standard SDRAM. Prefetch allows multiple bits to be fetched in parallel per clock cycle: DDR1 uses 2n prefetch, DDR2 uses 4n, DDR3/DDR4 use 8n. For a DDR3 16-bit SDRAM chip, one read/write accesses 8 × 16 = 128 bits.

Frequency concepts: Core frequency is the memory cell array operating frequency. DDR1 core frequency equals clock frequency. DDR2/DDR3 introduced clock frequency as a multiplied version of core frequency. Data transfer frequency (MT/s) is twice the I/O clock frequency due to double-edge transfer.

DDR Subsystem Architecture

The DDR subsystem comprises DDR Controller (DDRC), DDR PHY, and SDRAM chips. DDR IP includes Controller and PHY. Key internal functions: data ordering, arbitration, optimal scheduling, protocol state machine design, starvation prevention, bypass paths, fast frequency switching, and DDR training.

DDR Working Principle

When clock pulses reach a certain frequency, DDR memory begins operation with a "read-store-read" cycle. The chip fetches data from the controller, stores it in the storage array, then retrieves and transmits it back to the processor. Double data rate means each clock cycle completes both "read-store" and "store-read" operations. DDR combines double data rate with multi-channel transmission and data verification for efficiency and reliability.

Key Components

Memory chips: Multiple chips per module, each with addressed storage cells.

Data bus: Connects to memory controller, transmits 64-bit or 128-bit data simultaneously.

Clock signal: Synchronizes operations; rising edge transfers data from chip to bus, falling edge transfers from bus to chip.

Precharge: Restores storage cell charge to initial state before data transfer for accuracy.

Data transmission: Multi-channel parallel transmission increases per-cycle data throughput.

DDR Interface Signals

Clock, address, and control signals are unidirectional from controller to DRAM. Strobe (DQS) and data signals are bidirectional: during reads, DQS and data flow from DRAM to controller; during writes, opposite direction. As speeds increase and signal amplitudes decrease, clock and strobe use differential signaling to eliminate common-mode noise; other signals remain single-ended and more susceptible to noise and crosstalk.

Memory Hierarchy

Internal memory (RAM): On motherboard, directly exchanges data with CPU; fast speed, small capacity.

External memory: Cannot directly exchange with CPU; slower, larger capacity; stores files, images, videos.

Cache: Buffer for data exchange; hardware checks cache first, then RAM; much faster than RAM.

Flash memory: Non-volatile, block-erase EEPROM variant; retains data without power; used for BIOS, PDA, digital cameras.

DDR Bandwidth Calculation

Bandwidth = Data Rate (MT/s) × Bus Width (bits) / 8. For example, DDR4-3200 (3200 MT/s) on 64-bit bus: 3200 × 64 / 8 = 25.6 GB/s.

SDRAM vs DDR

SDRAM (Synchronous DRAM) operates on rising clock edge only, with two interleaved arrays for efficiency. DDR is SDRAM's successor, using 2.5V (DDR1) to 1.1V (DDR5), transmitting on both clock edges, doubling transfer rate and bandwidth without raising clock frequency.

DDR4 vs DDR5 Detailed Comparison

DDR5 targets up to 8400 MT/s. Key improvements:

1.1 Speed Increase

DDR4 at 1.6 GHz clock reaches 3.2 GT/s. DDR5 starts at 4.8 GT/s (50% higher) and scales to 8.4 GT/s.

1.2 Voltage Reduction

VDD drops from 1.2V to 1.1V. Command/Address signals shift from SSTL to PODL, eliminating static power consumption at high logic levels.

1.3 DIMM Power Architecture

Power management moves from motherboard to DIMM via a 12V PMIC (Power Management IC) on the module, enabling finer-grained power control, improved signal integrity, and reduced noise.

1.4 DIMM Channel Architecture

DDR4 DIMM: 72-bit bus (64 data + 8 ECC). DDR5 DIMM: two independent 40-bit channels (32 data + 8 ECC each). Total data width remains 64 bits, but dual channels improve memory access efficiency and amplify throughput gains.

1.5 Longer Burst Length

DDR4 burst length: 4 or 8. DDR5 extends to 8 and 16 (BL16). BL16 enables single-burst access of 64 bytes — typical CPU cache line size — using only one of two channels, greatly improving concurrency and memory efficiency.

1.6 Larger DRAM Capacity

DDR4 max single-die package (SDP): 16 Gb. DDR5 SDP: up to 64 Gb, enabling DIMM capacities up to 256 GB (4× increase).

DDR5 Physical Layer Characteristics

1. Separated Full-Rate Clock

DDR5 uses a dedicated clock for command signals and strobe for data. At 6400 MT/s, clock frequency reaches 3.2 GHz. Stricter jitter requirements and tighter timing constraints for command, data, and address signals.

2. Wider Bus with Single-Ended Signaling

Multi-drop architecture from RCD (Registering Clock Driver) chips. Blade servers may support 1000+ parallel data channels. Single-ended signaling at doubled rates introduces loss issues previously seen only in serial differential links, requiring loss analysis alongside traditional crosstalk concerns.

3. Bidirectional Multiplexed Data Bus

Read/write share the same bus via time-division multiplexing due to limited routing resources. Validation requires separate read/write signal isolation for compliance checking.

4. ISI Effects at Higher Rates

Burst DQS and DQ signals suffer increased Inter-Symbol Interference (ISI) in bandwidth-limited channels. DQS preamble, first burst bit show distinct effects. Impedance mismatches in parallel memory circuits (unlike serial links) worsen reflection-induced ISI.

5. Advanced Receiver Equalization

Above 3600 MT/s, DDR5 adopts DFE (Decision Feedback Equalization) — mature in high-speed serial links — instead of DDR4's CTLE (Continuous-Time Linear Equalizer). CTLE amplifies noise; DFE better handles reflection noise. Variable Gain Amplifier (VGA) configured via MR registers compensates channel loss. Oscilloscopes capture pre-equalization (TP1) signals; embedded software applies DFE algorithms to generate post-equalization eye diagrams. Reference clock derived from DQS. Eye testing now includes CMD/ADDR bus, not just DQ.

DDR Terminology Reference

DDR: Double Data Rate

SDRAM: Synchronous Dynamic Random Access Memory

DDR SDRAM: Double Data Rate SDRAM

Channel: One DDR controller with its own address, control, and data lines

DIMM: Dual Inline Memory Module; 64-bit data path; one channel can have multiple DIMMs

Rank: Chip group accessed simultaneously by one channel; chip width × chip count = 64 bits (e.g., 8 chips × 8-bit = 64-bit rank)

Chip: Individual DRAM die; 4/8/16-bit width; multiple chips form a rank

Bank: Logical concept; DDR4/DDR5 have Bank Groups; total banks = Bank Group × Bank

Row/Column Memory Array: Bank as 2D bit array; each bank outputs 1 bit; 8 banks = 8 bits

Voltage (VDDQ): Output buffer supply voltage

Device Width: Chip data width (x4/x8/x16); x4 outputs 4 bits per row/column access

Die Density: Chip capacity; increases per DDR generation

Data Rates (MT/s): Mega-transfers per second; DDR = 2× I/O clock frequency

Prefetch: Parallel fetch of adjacent column data; 2n/4n/8n bits per cycle

Bank Group: Bank grouping; DDR4/DDR5 only

Burst Length: Consecutive column accesses per burst; matches prefetch bits

Core Frequency: Cell array operating frequency; base for all other frequencies

I/O Clock Frequency: Data transfer rate; related to prefetch (DDR: 2-bit prefetch, DDR2: 4-bit, DDR3: 8-bit)

Arbitration CMD Priority: Cadence Denali controller example: Round Robin (per-port counters), Bandwidth Allocation/Priority Round Robin (priority groups, bandwidth limits), Weighted Priority Round Robin (QoS-oriented, weight-based frequency)

DDR SDRAM Control: Command queue with reordering algorithm considering address collision, source collision, data collision, command type, priority; command grouping and bank splitting for efficiency; out-of-order execution of lower-priority commands when higher-priority not ready; supports frequency scaling via registers

Transaction Processing: Reorders commands to maximize DRAM read/write bandwidth throughput