Industry Insights 12 min read

Eight Cutting-Edge Chinese AI Supernodes Revealed at WAIC 2026

The WAIC 2026 showcase introduced eight domestic AI supernodes—from Huawei’s 1024‑card Atlas 950 to New H3C’s scalable UniPoD S80000—detailing their card counts, interconnect bandwidth, FP8/FP4 performance, and how China’s AI compute evaluation is shifting from single‑chip peaks to system‑level efficiency and cost.

Architects' Tech Alliance
Architects' Tech Alliance
Architects' Tech Alliance
Eight Cutting-Edge Chinese AI Supernodes Revealed at WAIC 2026

Overview

Supernodes have become the common technical route for AI infrastructure in China. At WAIC 2026, major compute vendors displayed eight supernode products, expanding from single‑chip peak performance to a broader evaluation framework that includes bandwidth, software maturity, and system delivery capabilities.

1. Huawei: Ascend 950 Supernode

Huawei unveiled the Atlas 950 SuperPoD with 1024 NPU cards, delivering 1 EFLOPS FP8 and 2 EFLOPS FP4 compute, a 256 TB unified memory address space, and a 3 µs round‑trip time (RTT) interconnect, targeting trillion‑parameter model training and high‑concurrency inference.

2. ZTE: OEX Supernode

ZTE’s OEX supernode provides a unified interface compatible with multiple domestic GPUs, adopts a “three‑zero cable” design, and integrates chip, algorithm, chassis, cluster, and software through an “OEX compute container” to reduce product launch cycles and token cost while simplifying chip replacement and scaling.

3. MuXi: S600

The S600 cabinet uses 64 high‑density cards with full‑cabinet interconnect, dramatically lowering data‑exchange latency and improving parallel efficiency for large‑model training and inference. It supports EP, TP and other parallel strategies and can scale to ten‑thousand cards for massive AI centers.

4. Moore Threads: MTT C256

Moore Threads demonstrated the MTT C256, a 256‑GPU scale‑up network that integrates compute and exchange in a single layer to reduce bandwidth loss and forwarding latency. The system showcases model‑training, token‑generation, and agent‑load factories, highlighting the importance of switch‑chip port density and topology for efficiency.

5. Inspur: Sunway 8000 (DengFeng)

Inspur’s Sunway 8000 expands domestic compute systems to the hundred‑thousand‑card level, supporting FP64 to INT8 precision, connecting to the national super‑computing internet, and handling scientific computing, large‑model training, inference, and industrial simulation across more than 20 application domains.

6. Biren Technology: NPO Product Matrix

Biren introduced a next‑generation NPO optical‑interconnect architecture with the BR2xx GPU series, supporting FP8/FP4 low‑precision high‑throughput compute. The BLink2.0 protocol enables up to 1024 GPUs to share a unified memory space. Their three‑level matrix includes 16‑card standard servers, 128‑card high‑density cabinets, and 1024‑card distributed NPO nodes.

7. Suiyuan Technology: Dual 64‑Card Solutions

Suiyuan presented two 64‑card solutions—ESL64‑O (orthogonal architecture) and ESL64‑C (cable‑tray design)—targeting different data‑center conditions. Both support scaling beyond 512 cards, with the NPO prototype breaking traditional copper‑cable distance limits and enabling high‑bandwidth, low‑latency expansion.

8. New H3C: UniPoD S80000

New H3C’s UniPoD S80000 covers 32 to 1024 cards per cabinet and can elastically expand to 16 384 cards, delivering a 70% training performance boost and a three‑fold inference improvement. The solution integrates optical interconnect, AI‑network co‑optimization, high‑density architecture, and topology tuning to lower total cost of ownership across government cloud, AI training centers, and medical research.

Key Trends and Incremental Elements

The core incremental elements of supernodes are:

Exchange chips and switches: scaling from 8‑card to 1024‑card interconnects, increasing port counts, per‑port speeds, and switch capacity.

Servers and cabinets: moving from single white‑box servers to full‑cabinet and Pod‑level systems, raising power, cooling, interconnect, and system‑tuning complexity.

Connectors: increasing high‑speed links between compute boards, switch boards, power and backplane, with rising SerDes rates and parallel evolution of orthogonal, cable‑tray, and NPO architectures.

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HuaweiZTEAI supernodeMoore ThreadsInspurWAIC 2026Biren TechnologyNew H3C
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