Essential ARM Assembly Instructions Every Linux Developer Should Know

1. Data Processing Instructions

MOV transfers a value or immediate constant to a register.

MOV destination, source

MOV R1, R0   ; copy R0 to R1

ADD adds two operands and stores the result.

ADD Rd, Op1, Op2   ; Rd = Op1 + Op2

ADD R0, R1, R2   ; R0 = R1 + R2
ADD R0, R1, #256 ; R0 = R1 + 256

ADC adds two operands plus the carry flag. ADC Rd, Op1, Op2 SUB subtracts the second operand from the first.

SUB Rd, Op1, Op2   ; Rd = Op1 - Op2

SUB R0, R1, R2   ; R0 = R1 - R2
SUB R0, R1, #256 ; R0 = R1 - 256

CMP compares two values by subtracting them and setting CPSR flags.

CMP R1, R0   ; R1 - R0, update flags
CMP R1, #100 ; R1 - 100, update flags

AND performs a bitwise AND.

AND Rd, Op1, Op2   ; Rd = Op1 & Op2

AND R0, R0, #3   ; keep bits 0‑1 of R0, clear others

ORR performs a bitwise OR.

ORR Rd, Op1, Op2   ; Rd = Op1 | Op2

ORR R0, R0, #3   ; set bits 0‑1 of R0, leave others unchanged

2. Transfer (Branch) Instructions

B   label          ; unconditional branch
BL  label          ; branch with link (return address saved)
BLX target         ; branch with link and state switch
BX  register       ; branch to address in register, optional state switch

3. Program Status Register Access

MRS moves CPSR or SPSR contents to a general‑purpose register.

MRS R0, CPSR   ; read CPSR into R0
MRS R0, SPSR   ; read SPSR into R0

MSR writes a value to CPSR or SPSR.

MSR CPSR, R0   ; write R0 to CPSR
MSR SPSR, R0   ; write R0 to SPSR

4. Load/Store Instructions

LDR loads a 32‑bit word from memory into a register.

LDR R0, [R1]            ; load word at address in R1
LDR R0, [R1, R2]        ; address = R1 + R2
LDR R0, [R1, #8]        ; address = R1 + 8
LDR R0, [R1, R2]!       ; load then write back updated address
LDR R0, [R1, #8]!       ; load then write back R1+8

STR stores a 32‑bit word from a register to memory.

STR R0, [R1]            ; store R0 at address in R1
STR R0, [R1, #8]        ; store at R1+8
STR R0, [R1], #8        ; store then increment R1 by 8

5. Exception‑Generating Instructions

SWI triggers a software interrupt.

SWI 24   ; invoke OS routine number 24
SWI 0x02 ; invoke OS routine number 2

BKPT creates a breakpoint for debugging.

BKPT 16   ; breakpoint with immediate value 16

6. Pseudo‑Ops (Assembler Directives)

AREA defines a code or data segment.

AREA Init, CODE, READONLY   ; define a read‑only code segment named Init

ALIGN aligns the location counter to a power‑of‑two boundary. ALIGN { expression , offset } CODE16 / CODE32 switches the instruction set size.

CODE16   ; subsequent instructions are 16‑bit Thumb
CODE32   ; subsequent instructions are 32‑bit ARM

ENTRY marks the program entry point.

ENTRY
ENTRY(stext)   ; specify entry symbol

END indicates the end of the source file.

END