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This article explains the role of the interrupt system in ARM‑based Linux platforms, covering hardware modes, vector tables, exception handling, GIC architecture, and kernel integration, and provides detailed code examples and optimization techniques for developers working on embedded and high‑performance systems.
This article compares the major CPU instruction set architectures—x86, ARM, and RISC‑V—detailing their design philosophies, evolution, strengths, and weaknesses, while also summarizing recent updates in CPU, GPU, memory, and storage technologies and highlighting the trade‑offs between CISC and RISC approaches.
This article explains how modern multiprocessor hardware and compiler optimizations affect program behavior, introduces memory consistency models such as sequential consistency, x86‑TSO, and ARM/POWER weak models, demonstrates their differences with litmus tests, and discusses the DRF‑SC guarantee for data‑race‑free programs.
To reduce costs and boost compute density, iQIYI's big data team migrated from aging private‑cloud Intel servers to public‑cloud AMD and ARM bare‑metal instances, establishing a systematic machine‑selection process, performance testing framework, and YARN‑based heterogeneous scheduling to fully leverage the new hardware.
This tutorial walks you through checking the OS architecture, preparing the environment, downloading and extracting the MySQL 5.7 ARM package, configuring my.cnf, setting up auto‑start and environment variables, initializing the server, securing the root account, and configuring master‑slave replication on Linux.
The article explains that __disable_irq() and __enable_irq() are compiler‑provided intrinsics that expand to CPSID i and CPSIE i instructions, return the prior PRIMASK state, globally mask CPU interrupt handling without stopping hardware events, and contrasts them with CMSIS __NVIC_DisableIRQ/EnableIRQ which control individual interrupt lines.
The 2024 China server CPU industry overview analyzes the dominance of X86 and ARM ecosystems, presents market size growth from 2018 to 2028, examines competitive advantages of domestic vendors, and discusses policy-driven demand and pricing challenges shaping the domestic CPU market.
German Linux‑hardware maker TUXEDO unveiled its ARM‑based “Drako” laptop at Computex, featuring a Qualcomm Snapdragon X Elite 12‑core CPU, 14‑inch 2560×1600 IPS display, 32 GB LPDDR5x RAM and PCIe Gen4 SSD, running the KDE‑Plasma TUXEDO OS ported to ARM, with Qualcomm’s upstream Linux support and collaborations with Lenovo, Arm and Linaro, and the first units slated for delivery by the end of 2024.
The article details Qianxun's migration of its core location services to Alibaba Cloud's Yitian ARM-based ECS instances, covering preparation steps, performance benchmarks, cost‑benefit analysis, operational challenges, and future migration plans to improve efficiency and reduce expenses.
The Feitian Technology Salon held on May 16 in Shanghai showcased Arm Neoverse's core advantages and demonstrated how Yitian 710‑based ECS instances deliver significant cost‑effective performance gains for big‑data and video workloads through cloud‑native optimizations and software acceleration techniques.
From a rapid BBC Micro prototype in the early 1980s to the 1985 launch of the Acorn RISC Machine, ARM evolved into a low‑power, licensed CPU core that powered devices from the Newton to today’s iPhone, ultimately becoming the world’s most ubiquitous processor architecture.
This article provides a comprehensive overview of contemporary processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their design philosophies, historical evolution, advantages, disadvantages, and the current landscape of domestic and international CPU development.
This article explains how Linux kernel Oops messages are generated, their format, the relationship between BUG, Oops and panic, and provides step‑by‑step debugging methods with code examples for ARM, PowerPC and MIPS architectures.
This article presents a detailed performance comparison of cloud RDS MySQL services across major providers, examining x86 versus ARM architectures, various storage options, and cost‑performance ratios, and concludes with practical recommendations for choosing the most suitable configuration.
This article provides a comprehensive overview of modern processor instruction set architectures, comparing CISC‑based x86 with RISC‑based ARM and RISC‑V, discussing their historical development, design philosophies, advantages, disadvantages, and current market adoption in both domestic and global contexts.
The article provides a comprehensive overview of ARM's recent architectural advances—including the flexible EPYC design, the Neoverse platform, AWS Graviton processors, and the security‑focused Armv9 with AI‑optimized SVE2 and Confidential Compute—highlighting their impact on cloud, data‑center and edge computing.
This guide explains how to deploy the high‑performance MPP database StarRocks 3 on ARM servers by using Docker images, configuring FE and BE nodes, adjusting Java versions, integrating with Hadoop/Hive, and setting up monitoring and log‑cleanup scripts.
By converting the input format to a C16 layout and exploiting the ARM V8.2 Sdot instruction, the Int8 depthwise‑convolution operator on ARM CPUs can be accelerated from 4.46 ms to 1.75 ms—a 2.5× speedup—though the required data‑rearrangement overhead prevents it from overtaking FP16 performance.
The article explains the fundamental differences between ARM and x86 CPUs, compares RISC and CISC instruction set philosophies, discusses how each architecture balances transistor count, performance, power consumption and cost, and highlights why ARM dominates low‑power devices while x86 remains prevalent in high‑performance computers.
This guide outlines a systematic learning roadmap for mastering ARMv8 and ARMv9 architectures, covering GIC, exception handling, MMU, cache, TrustZone security, and exclusive mechanisms, and includes recommended course resources, difficulty levels, target audiences, and practical notes.