FPGA-Based High-Compression Image Encoding: Architecture, Optimization, and Performance Evaluation

Project Background

Most images on the Internet are still JPEG, but newer image/video codecs can achieve more than 50% higher compression ratios. Using such high‑compression formats on the client can cut bandwidth by over 50% and improve download experience. However, higher compression algorithms increase computational complexity, making CPU‑based encoding costly and hard to deploy at scale. Therefore, a hardware FPGA codec solution is proposed to improve computational efficiency and density, reducing hardware cost.

Development Implementation

The project is divided into two stages: Encoding Function Verification and Encoding Performance Enhancement .

Encoding Function Verification Phase runs the FPGA at 100 MHz to analyze encoding effect and image quality.

Encoding Performance Enhancement Phase raises the clock to 300 MHz and implements multiple parallel IP cores, aiming for a 25× performance gain compared with a CPU server.

Technical Hierarchy

The development involves FPGA logic development and software development. The FPGA acts as a co‑processor in a server, connected to the CPU via a PCIe card, and is built on the AliFPGA logical platform.

System Layer Structure

The overall architecture consists of three layers: FPGA Functional Logic Layer , AliFPGA General Development Platform , and Business Software Layer .

FPGA Functional Logic Layer implements the high‑compression image format encoding.

AliFPGA General Development Platform provides the interface between software and FPGA logic, including FPGA and driver parts; the driver offers command and data interfaces to the business software.

Business Software Layer handles network communication and business logic.

Key Optimization Points

High‑performance FPGA data processing requires consideration of system pipeline design, FPGA logic frequency increase, and software design.

FPGA Hardware Encoding Pipeline Optimization

Pipeline customization leverages FPGA’s independent hardware resources. By decoupling the standard encoding flow and splitting it from 2‑stage to 4‑stage pipelines, throughput doubled compared to the original flow.

Frequency Boost of FPGA Logic

Beyond pipeline techniques, raising the operating frequency of each IP core is crucial. The project runs the general logic platform at 250–300 MHz, with functional IP cores at 300 MHz. Critical path analysis and targeted optimizations (reducing unrelated logic coupling and improving register fan‑out) increased the image encoding core frequency threefold.

Software Design

The software layer dispatches raw image files to the FPGA encoder and returns encoded files to the scheduler. Design focuses on multi‑concurrency at the application layer, multi‑IP support in the driver layer, and load balancing across channels.

Performance Improvement

The FPGA‑based solution runs at 300 MHz with multiple parallel IP channels, achieving a 25× overall performance increase over a high‑performance 64‑core CPU server in real‑world tests.

Conclusion

Performance tests demonstrate that the FPGA codec outperforms traditional CPU solutions, suggesting broader adoption of FPGA‑based services to free CPU resources for other workloads.