This article explains the concept of computing power, its measurement units, classifications into general and specialized types, the role of CPUs, GPUs, FPGA and ASIC chips, and how it underpins AI model training, blockchain mining, and scientific research.
The article examines the limitations of traditional von‑Neumann CPUs and power‑hungry GPUs for modern AI workloads, explains the rise of ASIC and FPGA based AI accelerators, compares major industry solutions, and highlights why reconfigurable, low‑power AI chips are becoming essential for robotics and edge computing.
This article explains what ASIC chips are, how they differ from CPUs, GPUs and FPGAs, classifies them by customization level and function, outlines their performance and cost advantages, discusses their drawbacks, and reviews current products and market trends driving AI hardware adoption.
This article explains the rise of AI‑specific processors, defines AI chips, compares their architectures, and examines the distinct requirements of training versus inference chips while outlining the main technology routes (GPU, FPGA, ASIC) and future outlook.
The FlightVGM paper, awarded Best Paper at FPGA 2025, details a novel FPGA-based inference IP for video generation models that leverages time‑space activation sparsity, mixed‑precision DSP58 extensions, and adaptive scheduling to achieve up to 1.30× performance and 4.49× energy‑efficiency gains over a NVIDIA 3090 GPU while preserving model accuracy.
Broadcom’s market‑cap breakthrough past $1 trillion highlights its strategic push into AI ASICs, revealing how ASIC‑FPGA trade‑offs, collaborations with Google, and competition with Nvidia’s GPU ecosystem are reshaping the high‑performance computing landscape.
The article analyzes the limits of the von Neumann model and Moore's law, explains how instruction set complexity defines processor categories, and argues that integrating CPUs, GPUs, FPGAs, DPUs and ASICs into a super‑heterogeneous ecosystem—driven by Intel, NVIDIA, ARM and emerging trends—will shape the future of computing through diverse workloads, AI demand, green efficiency and a global compute network by 2030.
This article explains DMA fundamentals, compares Block DMA and Scatter‑Gather DMA step by step, and evaluates the open‑source RIFFA PCIe framework, including its hardware flow, software components, board‑level performance tests, features, drawbacks, and licensing terms.
While GPUs have driven AI acceleration for years, this article analyzes their architectural constraints, compares emerging alternatives such as Google's TPU and high‑end FPGAs, and explores future application niches like VR/AR, cloud gaming, and military systems where GPUs may still thrive or be replaced.
The talk examines the challenges of using standard Linux TCP for high‑performance data‑center workloads, explores how RDMA can provide zero‑copy and asynchronous kernel bypass, and presents experimental results from an FPGA‑based prototype that approaches 800 Gbps packet rates while highlighting congestion‑control and CPU‑utilization trade‑offs.
The article examines Nvidia's GH200 superchip and AMD's Instinct MI300, compares CPU, GPU, FPGA, and ASIC architectures, analyzes market share trends, and discusses opportunities for domestic chip makers in the rapidly evolving AI compute landscape.
The article outlines the four evolutionary stages of network adapters—from traditional NICs to SmartNICs, FPGA‑based DPUs, and single‑chip DPU SoCs—explains their hardware features and offload capabilities, and surveys real‑world DPU deployments in AWS Nitro, Nvidia BlueField, Intel IPU, Alibaba Cloud CIPU, and Volcano Engine, highlighting their impact on data‑center performance, cost, and programmability.
The article analyzes the rapid growth of FPGA technology, its flexible architecture and low‑cost development, the expanding role of FPGA in data‑center acceleration, the strategic moves of AMD, Intel and Nvidia in heterogeneous computing, and forecasts a strong market expansion worldwide through 2025.
This article provides a comprehensive overview of FPGA technology, detailing its programmable logic cells, input/output blocks, switch matrices, historical evolution, flexibility versus ASIC and GPU, memory hierarchy including on‑chip and HBM2e, and the benefits of Network‑on‑Chip architectures for performance, power and design modularity.
The article analyzes the FPGA industry's two historical phases, compares international and Chinese vendors, examines product families, process technologies, market shares, demand trends, and highlights opportunities for domestic substitution and future growth in both hardware and software ecosystems.
AMD’s new Versal Premium VP1902 FPGA, the world’s largest adaptive SoC, doubles logic capacity over its predecessor, adds extensive high‑speed transceivers, NoC and PCIe upgrades, and promises faster debugging and AI‑driven chip validation, marking a significant shift in semiconductor prototyping.
The article reviews the DFX system—a multi‑FPGA server that uses model‑parallelism and a ring‑topology interconnect to accelerate GPT‑2 text generation, showing 3.78× higher throughput, 3.99× better energy efficiency, and 8.21× greater cost‑effectiveness compared with a four‑GPU V100 baseline.
The article analyzes the limitations of traditional X86‑based software load‑balancing gateways and presents Baidu Cloud’s third‑generation UNP programmable platform, detailing its heterogeneous architecture, fast‑path/slow‑path processing, performance gains, a real‑world case study, and future roadmap.
This article explains what FPGA chips are, how they differ from CPUs, GPUs and ASICs, describes their internal programmable architecture and LUT-based logic, highlights their short development cycle and parallel computing benefits, and provides a detailed market analysis of Chinese FPGA applications and future growth prospects.
The article analyzes how GPUs, once dominant in accelerating AI workloads, now face limitations in precision, energy efficiency, and on‑chip networking, prompting a shift toward specialized accelerators like Google's TPU and FPGA solutions, while also exploring emerging GPU‑friendly scenarios such as VR/AR, cloud gaming, and military applications.
This article provides a comprehensive introduction to programmable logic devices, covering their origins, classification, development history, internal architectures of CPLD and FPGA, and the essential EDA tools and IP cores needed for modern digital hardware design.
This article explains how high‑frequency trading firms achieve ultra‑low network latency by combining proximity deployment, dedicated links, microwave transmission, InfiniBand, low‑latency switches, kernel bypass, RDMA, TCP offload engines and FPGA acceleration, and summarizes the impact of each technique on overall request latency.
This article provides a comprehensive comparison between FPGA and ASIC, covering their architectures, design processes, speed, area, power consumption, cost factors, typical use cases, and emerging integration trends to help engineers decide which technology best fits their project requirements.
This article provides a detailed, line‑by‑line analysis of a chart comparing FPGA and ASIC across dimensions such as upfront costs, unit cost, time‑to‑market, performance, power consumption, field updates, density, design flow, granularity, verification needs, upgrade paths, and additional features, helping engineers decide which technology best fits their high‑performance AI workloads.
The article outlines FPGA's strong performance and versatility, presents recent market growth figures and drivers, explains the basic architecture and firmware development process, and highlights key applications in automotive, communications, and computer‑vision systems, emphasizing its expanding role in AI and deep‑learning solutions.
Tencent’s hardware teams evolved from a lack of verification tools in 2019 to building AI inference chips, video‑encoding silicon, and intelligent NICs, overcoming FPGA challenges, scaling cloud infrastructure, and delivering high‑performance, low‑cost solutions for massive multimedia and AI workloads.
The ISCA 2022 full‑score paper “Fidas: Fortifying the Cloud via Comprehensive FPGA‑based Offloading for Intrusion Detection” presents a novel FPGA‑accelerated IDS architecture that jointly offloads regex matching and traffic classification, achieving high flexibility, rapid rule updates, balanced load, and line‑rate performance in cloud data centers.
The article provides a comprehensive overview of AI chip technology, describing the dependence on mathematical models and semiconductor integration, classifying chips by architecture (GPU, FPGA, ASIC, SoC, brain‑like), deployment (cloud, edge, terminal), and outlining current challenges, market trends, and future research directions such as in‑memory and neuromorphic computing.
The article provides a comprehensive overview of AI chips, explaining their broad and narrow definitions, core architectures such as GPU, FPGA, and ASIC, deployment scenarios from cloud to edge, training versus inference roles, current market dynamics, major vendors, and emerging application domains like autonomous driving and smart security.
This article examines how FPGA accelerators handle compute‑intensive and communication‑intensive workloads, compares their performance and latency to CPU and GPU solutions, explores various deployment models in data centers, and outlines the evolving Chinese and global FPGA market landscape.
The article provides a comprehensive overview of AI chips—including GPUs, FPGAs, and ASICs—their architectural distinctions, cloud and edge deployment models, market dynamics in China, and key application scenarios such as autonomous driving, smart security, and IoT devices.
On February 14, AMD completed its landmark $35 billion all‑stock purchase of Xilinx, a move that expands AMD’s product portfolio with FPGA and adaptive SoC technologies, strengthens its position in AI, data‑center and edge markets, and signals a strategic push to compete with Intel.
This article provides a detailed, line‑by‑line comparison of FPGA and ASIC across pre‑fabrication cost, unit cost, time‑to‑market, performance, power consumption, field update capability, density, design flow, verification, upgrade paths, and the role of structured ASICs, helping engineers decide the optimal solution for complex, high‑performance, non‑standard IC designs.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends showing rising shares of MPU and logic chips, declining DRAM, stable analog and MCU, and details the market status, growth forecasts, and challenges for CPU, GPU, FPGA, ASIC, and storage technologies.
This article reviews the OSDI20 best paper on hXDP, explaining why combining XDP with FPGA NICs can alleviate CPU bottlenecks, describing the challenges of eBPF offload to low‑frequency FPGA, and summarizing the custom instruction‑set optimizations and test results that achieve comparable performance to multi‑GHz CPUs.
The 2021 China Integrated Circuit Market Research Report analyzes recent three‑year trends, showing rising shares for MPU and logic chips, declining DRAM, stable analog and MCU, while detailing the market positions, growth rates, and challenges of CPU, GPU, FPGA, ASIC, and flash storage technologies.
The article examines how FPGA’s pipeline parallel architecture provides latency‑critical advantages over CPU and GPU for both compute‑intensive workloads such as matrix operations and AI inference, and communication‑intensive tasks like encryption and high‑throughput networking, while also discussing deployment models, power efficiency, eFPGA trends, and the evolving Chinese FPGA market.
Data Processing Units (DPUs) have evolved from early I/O processors to modern programmable ASICs and FPGA-based accelerators, integrating networking, storage, and compute functions to offload workloads from CPUs, with contributions from companies like Fungible, Nvidia, Intel, and emerging Chinese firms, shaping data‑center and edge architectures.
The article examines edge computing hardware architecture, discussing diverse use cases, evolving server and processor trends—including ARM, Intel, Nvidia, AMD, FPGA, and DPU—open hardware standards, reliability, virtual networking, and storage innovations, highlighting how these developments shape the future of cloud and edge infrastructures.
The article explains how artificial intelligence relies on algorithms, compute and data, compares engineering and simulation methods, and details the roles, architectures, performance and energy characteristics of GPUs, FPGAs, and ASICs as the primary hardware accelerators for modern deep‑learning applications.
Smart NICs offload networking, storage, and security workloads from host CPUs, leveraging multi‑core ASICs, FPGA, and hybrid designs to boost throughput, reduce latency, and enable programmable data‑plane functions, making them essential for modern cloud, SDN, NFV, and hyper‑converged data‑center architectures.
The article examines how AMD, NVIDIA, and Intel are expanding their high‑performance computing portfolios through acquisitions and product development, focusing on FPGA, AI accelerators, and cloud‑centric strategies, and evaluates the technical and market implications of these moves.
The article outlines the classification of AI chips—including CPU, GPU, FPGA, and ASIC—explains FPGA's semi‑custom nature, its advantages over fully custom ASICs, and highlights its key applications in AI, autonomous driving, 5G communications, industrial IoT, and data centers.
The article explains the different types of AI chips, focuses on FPGA technology, its advantages, market landscape, and its applications in cloud and edge AI inference, while also highlighting Intel's Agilex FPGA and the growing demand for reconfigurable hardware in AI workloads.
The article examines the rapid growth of data‑center workloads, explains why heterogeneous accelerators such as CPUs, GPUs, FPGAs and ASICs are needed, outlines evaluation standards, compares their compute performance and power efficiency, and discusses practical deployment cases and future trends.
This article provides a comprehensive overview of ASIC chips, detailing their definition, material composition, classification by customization level and function, key advantages and disadvantages, and notable product examples across AI, security, and consumer electronics domains.
This article provides a comprehensive overview of FPGA technology, covering its definition, evolution, major manufacturers, internal architecture, development workflow, usage scenarios, and challenges, illustrating its role in fields such as data centers, AI, and telecommunications.
This article provides a comprehensive overview of the AI chip ecosystem, covering the evolution of GPU, FPGA, ASIC and neuromorphic chips, their performance trade‑offs, key industry players, and the rapid growth of China’s domestic chip manufacturers in the context of deep‑learning demands.
The article provides a comprehensive overview of SmartNICs, describing their three main architectures—multicore ASIC, FPGA‑based, and FPGA‑enhanced—detailing performance benefits, design trade‑offs, and example feature extensions for modern data‑center networking workloads.
The article defines SmartNICs, outlines their key capabilities such as off‑loading processing to programmable hardware, compares major vendor implementations—including Broadcom, Nvidia/Mellanox, Intel, Xilinx, Netronome, and Pensando—and discusses market trends that position SmartNICs as the next wave of FPGA‑based acceleration for data‑center workloads.
The article explains how SmartNICs—available as multi‑core ASIC, FPGA‑based, or FPGA‑enhanced designs—offload networking, storage, and compute tasks from CPUs, improve bandwidth and power efficiency, and outlines their architectural forms, development methods, and example feature extensions for modern data‑center environments.
The article provides a comprehensive overview of FPGA technology, detailing its architecture, advantages over ASICs, current global market size, growth drivers such as 5G and AI, and the challenges and opportunities faced by domestic Chinese manufacturers in a market dominated by Xilinx and Intel.
This article surveys the rapid rise of AI chips, explains why traditional CPUs fall short for deep learning, compares GPU, FPGA, and ASIC designs, outlines market dynamics in the US and China, and highlights emerging opportunities for specialized ASICs in mobile and edge applications.
The article provides a comprehensive overview of heterogeneous computing, detailing its definition, real‑world system examples, performance advantages, key programming frameworks such as OpenCL and CUDA, industry trends like SOC integration, and a comparative analysis of CPUs, GPUs, FPGAs and ASICs.
This article analyzes how system architects can select the optimal heterogeneous compute cores—CPU, GPU, FPGA, ASIC, VPU, or TPU—for edge AI deployments, weighing performance, size, weight, power, and cost to maximize inference efficiency and security.
The article reviews Azure's shift from pure software and ASIC networking to an FPGA‑based data‑plane solution, outlining the design motivations, comparing ASIC, multicore NIC, CPU, and FPGA approaches, addressing common FPGA concerns, and presenting performance results that show significant latency and throughput improvements over traditional software stacks.
This article explains heterogeneous computing and compares major processing units—CPU, GPU, FPGA, ASIC, and NPU—highlighting their architectures, strengths, and typical use cases, especially in deep‑learning and AI workloads.
FPGA, a reconfigurable hardware architecture, offers low latency and high efficiency compared to CPUs, GPUs, and ASICs, making it ideal for both compute‑intensive and communication‑intensive tasks, and Microsoft’s multi‑stage data‑center deployments illustrate its scalability, flexibility, and impact on cloud services.
This article provides a comprehensive overview of FPGA technology, its architectural components, advantages over ASICs, current global and Chinese market sizes, growth drivers such as 5G and AI, and the challenges and prospects for domestic FPGA manufacturers.
The article examines the evolving roles of FPGA, ASIC, and DSP in semiconductor technology, highlighting how advances in FPGA have reduced cost and power, enabling it to challenge ASIC and DSP markets, while discussing their distinct strengths, development flows, and the likely coexistence of these three technologies in the future.
This article provides a comprehensive overview of FPGA technology, covering its definition, historical development, major manufacturers, internal architecture, design flow, usage steps, and typical application scenarios in fields such as AI, telecommunications, and cloud computing.
The article reviews the evolution of artificial‑intelligence hardware, comparing traditional CPUs with parallel GPUs, reconfigurable FPGAs, fully custom ASICs, and emerging neuromorphic chips, highlighting their architectures, performance trade‑offs, power consumption, and current industry adoption.
This article compares various AI server architectures—CPU, GPU, FPGA, TPU, and ASIC—by evaluating performance versus programmability, and outlines practical guidelines for choosing GPU servers based on workload, cost, power, and deployment scenarios.
Alibaba Entertainment’s 2019 Double‑11 Cat Night live stream combined FPGA‑based H.265 transcoding, smart‑profile QoE adaptation, Dolby Atmos audio and frame‑aligned multi‑view video to deliver ultra‑HD 4K60 streams at 35% lower bandwidth cost, achieving zero failures, zero degradations and over 99.99% service availability.
The article explains how SmartNICs offload networking, storage, and compute tasks from CPUs to improve server performance and reduce power consumption, outlines three SmartNIC architectures—multicore ASIC, FPGA‑based, and FPGA‑enhanced—and details design methods and functional extensions illustrated with thirteen practical examples.
The article surveys the evolution of artificial‑intelligence chips, comparing traditional CPU architectures with parallel accelerators such as GPUs and FPGAs, fully custom ASICs, and emerging neuromorphic chips, highlighting their structures, performance trade‑offs, and application scenarios.
This article traces the development of automotive electronic control units from early CPU‑centric ECUs to centralized domain controllers, examines the rise of GPU‑based AI accelerators for assisted driving, and explains why ASICs are expected to dominate future autonomous‑driving chips, while profiling key industry players and their strategies.
This article explains what FPGA (Field‑Programmable Gate Array) is, why it offers lower latency and higher energy efficiency than CPUs or GPUs for both compute‑intensive and communication‑intensive workloads, and details Microsoft’s three‑generation FPGA deployment strategy in its data‑center and cloud infrastructure.
The article explains how heterogeneous parallel computing—distributing tasks across CPUs, GPUs, FPGAs and other accelerators—has become essential after Moore’s law plateau, detailing its principles, hardware and software perspectives, classification of architectures, processing stages, user‑guided versus compiler‑guided methods, and its relevance to AI, cloud and industry workloads.
This article provides a comprehensive overview of FPGA technology, covering its definition, historical development, major manufacturers, internal architecture, development workflow, challenges, and typical application scenarios such as data centers, telecommunications, and AI acceleration.
The article explains the principles of bilinear interpolation, why it is needed for smooth image scaling in neural‑network layers such as Interp and Resize, and details FPGA‑specific optimizations—including lookup‑table based coefficient pre‑computation, two‑line BRAM caching, and index‑driven data swapping—to reduce DSP usage and improve throughput.
This article examines how recent hardware advances such as multi‑core processors, large memory, SSDs, NVM, GPUs and FPGAs have reshaped database system design, outlines the stages from pure academic research to productization, and surveys current database products and research directions leveraging these new devices.
The article provides a comprehensive overview of FPGA technology, its hardware architecture, advantages over ASIC, and its expanding role in 5G, AI, automotive, and data‑center applications, while analyzing global market dynamics, domestic challenges, and future development trends.
The article provides a detailed, English-language overview of the entire integrated circuit design flow—from architecture and algorithm selection through RTL coding, verification, synthesis, layout, and sign‑off—highlighting the roles, tools, and challenges faced by engineers in modern ASIC and FPGA development.
This article provides a detailed introduction to Field‑Programmable Gate Arrays (FPGA), covering their definition, evolution, major vendors, internal architecture, design and programming workflow, usage in data‑center and telecom, and typical application scenarios such as AI and high‑performance computing.
The article reviews the two main development routes for artificial intelligence chips—traditional architectures that enhance CPU, GPU, and FPGA performance and emerging neuromorphic designs like IBM TrueNorth—detailing their structures, advantages, limitations, and industry adoption.
This article compares CPU, GPU, FPGA, TPU, and ASIC based AI servers on performance and programmability, explains selection factors such as power, cost, precision, and memory, and provides practical guidelines for choosing appropriate GPU server architectures and models.
The OpenStack Cyborg project provides a generic framework that lets cloud platforms discover, schedule, and control proprietary accelerators such as GPUs, FPGAs, ASICs and SoCs, solving resource waste in AI, NFV, edge and HPC workloads.
Alibaba unveiled an FPGA‑designed machine‑learning accelerator that achieves sub‑millisecond inference latency and thousands of frames‑per‑second throughput, demonstrating how integrated hardware‑software optimizations can deliver real‑time AI performance surpassing conventional GPU and ASIC solutions.
In his 2018 Trusted Cloud Conference talk, Tencent FPGA expert Zhang Heng explained how the rapid growth of data and AI workloads drives data‑center and cloud operators to adopt FPGA acceleration for its high‑throughput, low‑latency, programmable performance, citing Tencent’s successes in image transcoding, content‑moderation, AI inference and gene‑sequencing, while outlining ecosystem challenges and future plans for scalable cloud‑FPGA services.
Alibaba Cloud introduces the F3 FPGA instance, a dual‑chip VU9P‑based accelerator that combines a unified HDK/SDK platform, secure IP marketplace, and ultra‑high‑speed interconnects to make FPGA acceleration more accessible, flexible, and cost‑effective for cloud users.
The article explains how heterogeneous parallel computing—leveraging CPUs, GPUs, FPGAs and other specialized units—addresses the performance limits of traditional serial programming by distributing tasks across diverse hardware, detailing its concepts, architectures, development models, and relevance to AI and cloud workloads.
This article presents the design, implementation, and evaluation of X‑Engine, a next‑generation LSM‑Tree based storage engine that offloads compaction to FPGA, achieving up to 50% KV‑interface and 40% SQL‑interface performance gains for write‑intensive OLTP workloads.
This article introduces Alibaba’s X‑Engine storage engine, the foundation of the next‑generation distributed database X‑DB, and explains how FPGA‑accelerated compaction and asynchronous scheduling dramatically improve write‑intensive OLTP performance, reduce CPU contention, and achieve up to 50 % throughput gains while maintaining fault tolerance.
This article describes a project that replaces CPU‑based image compression with an FPGA solution, detailing the system hierarchy, two‑phase development (function verification and performance boost), pipeline and frequency optimizations, software‑FPGA interaction, and a measured 25‑fold speedup over a 64‑core server.
The article explains why general‑purpose CPUs can no longer meet deep‑learning demands due to intrinsic scaling limits and memory‑bandwidth bottlenecks, and surveys how heterogeneous accelerators—GPUs, FPGAs, ASICs and emerging AI processors with high‑bandwidth memory—provide specialized, high‑parallelism, power‑efficient solutions for both cloud and edge workloads.
This article reviews various architectural strategies—including streaming processing, on‑chip memory optimization, bit‑width compression, sparsity techniques, on‑chip models with chip‑level interconnects, and emerging technologies such as binary networks, memristors, and HBM—to alleviate bandwidth bottlenecks in FPGA/ASIC/TPU AI accelerators.
The article analyzes the limitations of general‑purpose CPUs for deep‑learning workloads, explains how semiconductor scaling and memory‑bandwidth constraints drive the shift toward specialized heterogeneous processors such as GPUs, FPGAs, and ASICs, and discusses the design trade‑offs of embedded versus cloud AI accelerators.
This article presents a comprehensive overview of a universal FPGA‑based CNN accelerator, detailing its motivation, flexible architecture, compiler workflow, memory and compute unit designs, and performance comparisons that demonstrate significant latency and cost advantages over CPU and GPU solutions for real‑time AI inference.
Tencent Cloud’s FPGA service brings ASIC‑level performance with CPU‑like flexibility to AI workloads, cutting deployment time from months to minutes, delivering up to 30× CPU speed, 20‑100× latency reductions and 3‑5× throughput gains while lowering costs through pay‑as‑you‑go cloud access.
