How Alibaba Cloud’s New F3 FPGA Instance Revolutionizes Cloud Acceleration

FPGA (Field‑Programmable Gate Array) offers parallel hardware acceleration and programmability, but its high development barrier has kept it out of mainstream use.

Alibaba Cloud’s heterogeneous computing and high‑performance computing teams aim to democratize compute resources; the FPGA‑as‑a‑Service (FaaS) platform provides on‑demand Intel and Xilinx FPGA instances (F1, F2) and now the large‑scale F3 instance based on Xilinx 16 nm Virtex UltraScale+ VU9P.

FaaS

FaaS delivers a unified hardware platform and middleware in the cloud, lowering development and deployment costs for accelerators. Developers can offer their accelerators as services, while users can consume them without needing to understand the underlying hardware.

HDK

The Hardware Development Kit (HDK) supplies a standardized FPGA hardware interface, handling high‑speed PCIe, SERDES, DDR controllers, and ensuring security isolation and stability. HDK consists of a static Shell and a dynamic Role , allowing flexible logic updates while keeping the Shell lightweight and reliable.

SDK

The Software Development Kit (SDK) complements HDK with host‑side drivers, libraries, and the faascmd management suite.

Host drivers and software libraries corresponding to the Shell+Role.

FPGA management tool faascmd for secure image generation, download, status query, and isolation of user operations.

FaaS IP Market

The IP market lowers the entry barrier by offering ready‑to‑use FPGA IP with strong isolation: IP owners and users never see each other’s netlists, and all transfers are encrypted, preventing piracy. Future plans include KMS‑based encryption for IP files, ensuring traceable and secure usage.

F3 Hardware Architecture

The F3 instance uses a single‑board dual‑chip VU9P design, delivering up to 16 VU9P chips per instance for high compute density and lower cost per performance.

A custom 600 Gb/s FPGA Link interconnect enables ultra‑low‑latency communication between the two chips, far surpassing typical 100 Gb/s data‑center links.

Each FPGA is paired with 64 GB DDR memory (one 16 GB channel always resident, three optional 48 GB channels) and can interconnect with other boards via 400 Gb/s Ethernet using Xilinx MAC cores, supporting mesh or ring topologies.

F3 Logic Structure

Shell provides static PCIe, management, and DDR interfaces that users cannot modify. Role resides in the dynamic region, supporting both OpenCL and RTL custom logic, and can be swapped as needed.

Role internal components include Interconnect (four DDR channels and clock domain isolation), Inter‑chip interconnect, Card interconnect, Custom Logic (using AXI‑4 and AXI‑Lite), DMA engines, and interrupt handling.

These features together make FPGA acceleration on Alibaba Cloud more accessible, secure, and versatile for a wide range of applications.