How the S3C2410/2440 PLL Generates CPU and USB Clocks

Phase‑Locked Loop (PLL) technology synchronises an external reference clock with an internal oscillator, allowing devices to generate stable internal frequencies required for correct memory access and peripheral operation.

In the Samsung S3C2410/2440 processors there are two PLLs: the machine PLL (MPLL) for the CPU and system buses, and the USB PLL (UPLL) for the USB clock. MPLL generates three main clocks: FCLK (CPU core clock), HCLK (AHB bus clock) and PCLK (APB bus clock).

FCLK drives the ARM920T core; HCLK supplies the high‑performance AHB bus used by memory controller, interrupt controller, LCD controller, DMA, and USB host; PCLK clocks peripheral interfaces such as WDT, I2S, I2C, PWM, MMC, ADC, UART, GPIO, RTC and SPI.

Typical division ratios for these clocks are 1:4:8 or 1:3:6. For example, with a main frequency (FCLK) of 400 MHz, HCLK would be 100 MHz and PCLK 50 MHz under a 1:4:8 setting.

The MPLL output frequency is calculated by: MPLL = (2 * m * FIN) / (p * 2^s) where m = MDIV + 8, p = PDIV + 2, and s = SDIV. The register MPLLCON stores the MDIV, PDIV and SDIV values. Using FIN = 16.9344 MHz, MDIV = 110, PDIV = 3, SDIV = 1 yields FCLK ≈ 399.65 MHz.

The USB clock is produced by a second PLL (UPLL). Its frequency is given by: UPLL = (m * FIN) / (p * 2^s) with the same definitions for m, p and s. The CLKDIVN register’s third bit (DIVN_UPLL) selects the ratio between UPLL and the USB clock (UCLK); a value of 0 gives a 1:1 ratio when UPLL is already 48 MHz.

The clock and power‑management module consists of three parts: clock control, USB control, and power control. It provides four power modes:

Normal Mode : all peripherals enabled, highest current consumption; software can disable peripherals to save power.

Slow Mode : PLL disabled, CPU runs directly from the external clock, power consumption depends on external clock frequency.

Idle Mode : CPU clock (FCLK) stopped while peripheral clocks remain; an interrupt can wake the CPU.

Power‑off Mode : internal supply shut down except for the wake‑up domain; wake‑up occurs via external interrupt or RTC.

The CLKDIVN register defines the relationship among FCLK, HCLK and PCLK, while the primary clock source comes from an external crystal (XTAL) or an external clock (EXTCLK).