Why STM32’s PLL Keeps Running After HSE Failure and How to Fix It

A customer reported that on an STM32F103VDT6, disconnecting the external 8 MHz crystal did not trigger the external watchdog reset because the MCU’s PLL continued to generate a low‑frequency clock, but enabling the Clock Security System (CSS) and handling the NMI correctly resolves the issue.

CSSHSEPLL

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Why STM32’s PLL Keeps Running After HSE Failure and How to Fix It

ITPUB

Mar 19, 2017 · Fundamentals

How the S3C2410/2440 PLL Generates CPU and USB Clocks

This article explains the role of Phase‑Locked Loops in Samsung S3C2410/2440 chips, detailing how MPLL and UPLL produce the FCLK, HCLK, PCLK, and USB clocks, the register settings and formulas used, and the associated power‑management modes.

MPLLPLLS3C2410

0 likes · 6 min read

How the S3C2410/2440 PLL Generates CPU and USB Clocks