How UALink 2.0 and CXL Are Redefining AI Scale‑Up Interconnects

Overview

The 2026 Open AI Infra Summit highlighted advances in high‑speed interconnects and super‑node ecosystems for AI compute at megawatt to gigawatt scales. Key technical topics included the evolution of the UALink 2.0 protocol and the integration of CXL with UALink to address AI storage and memory bandwidth challenges.

UALink 2.0 Protocol Evolution

The UALink Alliance, comprising more than 120 member companies, defines a memory‑centric, low‑latency Scale‑Up interconnect for AI accelerators that complements PCIe, CXL and Ethernet. Specification milestones:

April 2025 – 200 G V1.0

September 2025 – 128 G DL/PL V1.0

Early April 2026 – four new specifications completing the stack.

Key features of the UALink 2.0 universal specification:

In‑Network Compute : collective‑communication operations are offloaded to the fabric, reducing distributed‑training latency and bandwidth consumption.

200 G DL/PL 2.0 : separates data‑link and physical layers; introduces Link Resiliency and Link Folding for fault tolerance and topology flexibility.

Manageability Spec 1.0 : adds a centralized control plane using standard protocols gNMI, YANG, SAI and Redfish.

Chiplet Spec 1.0 : fully compatible with UCIe 3.0, simplifying integration with existing chiplet ecosystems.

These enhancements aim to meet the bandwidth and latency requirements of large‑model training and inference while providing an open standard for both domestic and global AI infrastructure.

CXL and UALink for AI Storage Scale‑Up

CXL provides memory consistency, high bandwidth and low latency by decoupling memory and enabling pooling. When combined with UALink, it creates a unified compute‑storage interconnect that eliminates the traditional storage‑compute gap.

Alibaba Cloud demonstrated three self‑developed CXL‑based solutions:

AliSCM : a persistent memory module offering larger capacity, lower cost, persistence, pooling, spatial isolation and rapid recovery.

AliFlash : a CXL storage product that exposes a KVCache directly to GPUs, markedly improving data‑access efficiency for large‑model inference.

Panjiu CXL memory‑pooling server : enables elastic scheduling and high‑utilization of pooled memory resources.

These components, together with the “compute‑storage‑in‑one” architecture built on CXL/UALink buses, provide ultra‑low‑latency intra‑rack links and high‑bandwidth cross‑rack access, satisfying the extreme bandwidth and latency demands of AI training and inference.

Test & Verification Services

The ODCC‑UALink test‑verification service, released jointly by ODCC and the UALink Alliance, allows members to validate IP, link protocols, transaction interactions and data transmission against the UALink 1.0 specification before silicon tape‑out. Early participants such as Nanfei Microelectronics, Hanbo Semiconductor, StarTech Microelectronics and Jiwei have completed IP‑level interoperability tests.

Outlook and Architectural Shift

Alibaba Cloud’s involvement in both the CXL and UALink alliances has led to concrete deployments:

First CXL memory‑pooling super‑node server, accelerating CXL adoption in cloud database workloads.

PolarDB GPU‑CXL memory‑pool direct‑connect architecture demonstrated in January 2024, enabling elastic scaling and cross‑machine memory sharing for large‑model inference.

Strategic guidance emphasizes moving from CPU‑centric interconnects to GPU‑centric architectures. By leveraging CXL for memory pooling and UALink for high‑performance GPU interconnect, the ecosystem aims to build AI‑native cloud infrastructure that can scale with the growing demands of massive AI models.