The PCI‑SIG has released the PCIe 8.0 draft (0.5), promising 256 GT/s (1 TB/s per x16 link) that doubles PCIe 7.0, remains backward‑compatible, and aims to eliminate the bandwidth bottleneck for AI, GPUs, SSDs and CXL, with a spec expected in 2028 and market rollout around 2029‑30.
At the 2026 Open AI Infra Summit, Alibaba Cloud showcased the evolution of the UALink 2.0 protocol and its integration with CXL, detailing new specifications, in‑network compute capabilities, and ecosystem developments that aim to overcome scale‑up bottlenecks in AI training and inference.
As AI, cloud, and 5G drive exponential data growth, traditional copper interconnects hit physical limits, prompting a shift to optical solutions—especially linear driver optics and UCIe standards—that promise higher bandwidth, longer reach, and better energy efficiency despite latency and power trade‑offs.
Alibaba Cloud's server R&D team presented three research papers at IEEE EPEPS 2024 and PCB West 2024 covering high‑density PCIe 6.0 crosstalk optimization, 100G‑PAM4 Ethernet performance under air and immersion cooling, and sustainable low‑cost PCB materials for immersion‑cooled computer systems, highlighting their relevance to AI infrastructure and data‑center design.
The rapid growth of AI models is widening the gap between compute power and memory bandwidth, but the emerging Compute Express Link (CXL) interconnect offers lower latency, memory sharing, and flexible device topologies that can alleviate the memory‑wall bottleneck and reshape future data‑center architectures.
Alibaba Cloud announced that two of its server‑R&D papers were selected for DesignCon and ECTC 2024, presenting measurement‑based studies on PCIe 5.0/6.0 link performance under air and immersion cooling and a long‑term reliability analysis of crystal oscillators in various immersion‑cooling fluids, insights that guide next‑generation server architecture and large‑scale liquid‑cool deployment.
Compute Express Link (CXL) is a high‑speed serial interconnect that bridges CPUs, accelerators, and memory to deliver higher bandwidth, lower latency, and flexible memory sharing, with detailed explanations of its background, three operational modes, benefits, use cases in data centers, AI, and challenges for implementation.
PCI‑SIG’s upcoming PCIe 7.0 specification, due in 2025, promises a raw 128 GT/s per lane and up to 512 GB/s bidirectional throughput on an x16 link, while introducing PAM4 signaling, shorter trace lengths, higher‑cost motherboards, and a roadmap that pushes market adoption to around 2028 for SSDs, GPUs and other devices.
Alibaba Cloud's infrastructure team presented three peer‑reviewed papers at DesignCon 2022, covering air‑cooled vs. immersion‑cooled 112 Gbps PAM4 interconnects, cost‑effective PCB manufacturing guidelines for immersion cooling, and signal‑integrity risks with DDR/PCIe Gen5 in liquid‑cooled server platforms.
