Intel’s World‑First 1.8nm Data‑Center CPU Packs 288 Cores – A Performance Leap

Intel’s 1.8nm Data‑Center CPU Breakthrough

At Computex 2026 Intel announced the first 1.8nm (18A) data‑center processor, the Xeon 6+ (code‑named Clearwater Forest), paired with a new Ethernet solution (E835) and an AI‑oriented data‑center GPU (Crescent Island).

1. Data‑Center Performance Ceiling

Previous CPUs either had few cores with weak compute or many cores with prohibitive power consumption. Intel’s Xeon 6+ addresses both by shrinking the process, stacking the die, and increasing core count while cutting power.

2. 1.8nm Process Innovations

RibbonFET (surround‑gate transistor) : replaces planar transistors with a 3‑D ring‑shaped gate, allowing more transistors per area, faster switching and lower leakage. Claimed gain: same power → 4 % performance increase; same performance → 10 % power reduction.

PowerVia (back‑side power delivery) : moves power routing to the backside of the chip, separating it from signal routing. This halves internal latency and improves energy efficiency by 23 %.

3. 3D Chiplet Stacking Architecture

To fit 288 cores on a “nail‑size” die, Intel uses a hybrid Foveros Direct 3D stack combined with EMIB 2.5D interconnect, creating a three‑tier chiplet hierarchy:

Compute layer (top) : 12 compute tiles built on 18A, each containing 24 Darkmont efficiency cores – total 288 cores.

Cache / memory layer (middle) : 3 base tiles on Intel 3 process, providing 576 MiB LLC (5× the previous generation) and a 12‑channel DDR5 controller.

I/O layer (bottom) : 2 I/O tiles on Intel 7 process, offering 96 PCIe 5.0 lanes (64 supporting CXL 2.0) for GPU, NIC and storage connectivity.

The stack uses copper‑to‑copper direct bonding with a 9 µm pitch, ten times faster and lower‑power than traditional packaging, while EMIB bridges enable high‑bandwidth, low‑latency communication across the stack.

4. Core Specifications and Performance

Core count : 288 cores per socket, 576 cores in dual‑socket servers – the highest core count for an x86 server CPU.

Cache : 576 MiB LLC + 288 MiB L2 cache (total 864 MiB), five times more than the prior generation.

Memory : 12‑channel DDR5‑8000 MT/s, delivering ~50 % higher bandwidth than the previous platform.

PCIe : 96 PCIe 5.0 lanes, 64 CXL 2.0 lanes for extensive expandability.

Benchmarking shows the Xeon 6+ delivers 2.26× overall performance and 1.55× performance‑per‑watt versus the Sierra Forest predecessor, with the same power envelope (330‑450 W) – a 38 % power reduction for equivalent compute. In virtualization, per‑thread performance is 1.3× higher, and cryptographic workloads see a 15× boost over the prior generation and a six‑fold advantage over competing CPUs.

5. Security and Energy‑Efficiency Enhancements

SGX (Software Guard Extensions) : provides a minimal trusted execution environment for data encryption and isolation.

TDX (Trusted Domain Extensions) : encrypts VM memory, enhancing multi‑tenant privacy in cloud workloads.

AET (Application Energy Telemetry) : monitors CPU power in real time, automatically throttling under low load to improve efficiency; full‑load performance‑per‑watt improves by 1.3×.

6. Complementary Ecosystem

Intel pairs the CPU with a “full‑stack” of accessories:

E835 200 GbE Ethernet : up to 200 Gbps bandwidth, configurable for 2×25G, 4×25G, 2×100G or 1×200G; power consumption 28‑47 % lower than rivals, delivering 1.4‑1.9× performance‑per‑watt.

Crescent Island GPU : first Xe3P architecture, optimized for long‑context large models; 480 GB LPDDR memory, 350 W TDP, fan‑cooled for existing data‑center racks; supports FP64 native compute.

Combined, a single Xeon 6+ can match the performance of two prior‑generation CPUs while using 38 % less power, halving server count, space, electricity and operational costs.