Kirin 9050 Pro Die Shot Analysis: 3D Stacking with Hybrid Bonding & LogicFolding Architecture

Physical Parameters of the Kirin 9050 Pro Dies

The Kirin 9050 Pro employs a dual-die structure with two identical dies each measuring 120.65 mm², yielding a total die area of approximately 241.3 mm². This represents a ~70% increase over the Kirin 9030 Pro's single-die area of 122 mm², while each individual die is slightly smaller.

Compute Die (Logic Die): Integrates CPU, Mali-G955 GPU, Da Vinci NPU, ISP, DSP, Balong modem, I/O controllers. Rumored to use SMIC N+3 process (unconfirmed).

SRAM Die: Contains all cache levels (L1/L2/L3, SLC). Rumored to use SMIC N+2 process (unconfirmed).

Interconnect: Copper-Copper Hybrid Bonding

The two dies are bonded face-to-face using hybrid bonding with approximately 5 million vertical interconnect contacts, achieving a cross-die bandwidth of 125 TB/s at micron-scale pitch — far exceeding traditional TSV density.

Key distinction: This is not merely cache stacking like AMD's 3D V-Cache. The LogicFolding (韬定律) approach splits a single pipeline across both dies during the design phase, enabling co-optimized layout and timing convergence — an architecture-level 3D reconstruction rather than simple package-level stacking.

Transistor Density

Combined dual-die transistor density reaches 238 million transistors/mm², a 55% improvement over Kirin 9030 Pro's 155 million/mm². The compute die alone shows ~28% density gain.

Die Partition Analysis (from Microscopy)

Compute Die Layout

Lingxi CPU 9-core cluster: 1× super core (3.13 GHz) + 2× performance cores (2.7 GHz) + 4× efficiency cores (1.75 GHz) + 2× ultra-low-power micro cores for background tasks. Supports SMT for 16 threads total.

Mali-G955 GPU: 62 compute units at 1050 MHz with hardware ray tracing. Occupies large upper-right region; identified as primary power hotspot. Each CU vertically connects to dedicated L1/L2 cache on SRAM die.

Da Vinci NPU (MoE architecture): 4-core array supporting on-device 30B-parameter models. Significantly larger area than 9030 Pro. High-density vertical interconnects to SRAM die drastically reduce weight-access latency for LLM inference.

ISP, DSP, Balong 5G-A Modem, MSP security processor: Positioned at die edges near I/O pads.

No large SRAM on compute die: All caches vertically accessed from SRAM die.

SRAM Die Layout

The SRAM die consists almost entirely of regular, repeating cache arrays with no large compute units. Each cache block aligns vertically with its corresponding compute module for near-zero vertical access distance.

GPU Multi-level SRAM: Per-CU L1 + shared 4 MB L2, vertically aligned with GPU.

CPU Caches: Private L1/L2 per super/performance core; shared L3 per cluster; separate blocks per cluster.

NPU Weight SRAM: 1 MB per core for weights/activations; critical for LLM inference.

ISP SRAM: Dual-core with 512 KB L2 for intermediate frames.

Modem + DSP/Display Cache: Balong modem 2304 KB; DSP/Display 512 KB.

SLC (System Level Cache): 12 MB unified shared cache accessible by CPU/GPU/NPU/ISP.

Hybrid Bonding Contacts: ~5 million Cu-Cu bonds distributing across surface; 125 TB/s bandwidth.

Cross-Section & Packaging (from Geekwan Teardown)

PoP Stack: Dual-die stack topped with LPDDR memory.

Face-to-Face Bonding: Compute die and SRAM die bonded metal-to-metal with Cu-Cu hybrid bonding layer; silicon substrates on outer sides.

Manufacturing Challenges: Micron-level wafer alignment; requires 3D-aware EDA tools for joint timing simulation, co-place-and-route, thermal simulation; vertical heat accumulation complicates thermal design.

Comparative Analysis: Kirin 9050 Pro vs. 9030 Pro vs. Snapdragon 8 Elite Gen5 (8E5)

Architecture: Kirin 9050 Pro uses LogicFolding dual-die face-to-face Cu-Cu hybrid bonding; 9030 Pro and 8E5 use traditional single 2D planar dies.

Die Count/Area: 9050 Pro: 2 dies, ~241.3 mm² total (Compute: N+3, SRAM: N+2). 9030 Pro: single die ~122 mm² (N+3). 8E5: single die ~126 mm² (TSMC N3P).

Transistor Density: 9050 Pro: 238 MTr/mm² (dual-die equivalent). 9030 Pro: 155 MTr/mm². 8E5: 190–210 MTr/mm².

Inter-die Interconnect: 9050 Pro: Cu-Cu hybrid bonding, 125 TB/s. Others: N/A (on-die metal).

CPU: 9050 Pro: Lingxi 9-core 4-cluster (1S+2P+4E+2 micro), SMT, 16 threads, 3.13 GHz max. 9030 Pro: Taishan 8-core 3-cluster (1S+3P+4E), 8 threads, 2.75 GHz max. 8E5: Oryon Gen3 8-core (2S+6P), 8 threads, 4.47 GHz max.

GPU: 9050 Pro: Mali-G955, 62 CU, HW ray tracing, 1050 MHz. 9030 Pro: Mali-G935, 56 CU, HW ray tracing. 8E5: Adreno 840, 12 MB GMEM, Tile Memory Heap.

NPU: 9050 Pro: Da Vinci MoE, on-device 30B params, vertical SRAM interconnect. 9030 Pro: Da Vinci single cluster. 8E5: Hexagon Fused AI, Micro Tile inference.

Cache Layout: 9050 Pro: All L1/L2/L3/SLC on separate SRAM die, vertical access. 9030 Pro: Caches co-located with compute on same die, SLC shared. 8E5: All caches on single die, includes dedicated GPU GMEM.

Core Conclusions & Technical Positioning

Advantages

Bypasses EUV constraints: Achieves density leap within DUV process ecosystem via 3D architecture innovation — a differentiated path for domestic semiconductors.

Memory wall mitigation: Massive vertical interconnects eliminate long planar wires, cutting access latency and power. NPU large-model inference benefits most.

Yield-friendly die sizes: Two ~120 mm² dies are easier to manufacture with higher yield than a single 240 mm² monolithic die.

Limitations

Design complexity explosion: Requires full 3D EDA flow (co-simulation, co-P&R, thermal, SI), increasing design cost and verification cycle.

Thermal coupling: Compute die heat conducts directly into SRAM die, demanding advanced thermal modeling and system-level cooling.

Hybrid bonding maturity: High process barrier; yield and reliability remain supply-chain challenges.