Master Layered and Time‑Slice Design for Microcontroller Projects

Layered Design Concept

Layered (or hierarchical) design separates a system into distinct levels—hardware, driver, and application—so that each layer hides the details of the lower one. This improves code reuse, portability, and maintainability, especially when pin assignments differ across boards.

Three‑Layer Keypad Example

The example uses a 4×4 matrix keypad. The hardware layer reads raw port values, debounces, and maps them to a KEY_DAT register. The driver layer operates only on KEY_DAT, providing a uniform interface and generating key‑event messages (press, release, long‑press, etc.). The application layer consumes those messages to implement specific functions without caring about the underlying wiring.

#define KEY_MIN  0x01
#define KEY_PLUS 0x01

unsigned char KeyDat;

void ReadPort(void) {
    if (P1 & KEY_PLUS == 0) {
        KeyDat |= 0x01; // map PLUS to bit0
    }
    if (P2 & KEY_MIN == 0) {
        KeyDat |= 0x02; // map MIN to bit1
    }
}

By changing only the ReadPort function, the same driver and application code can run on boards with completely different pin layouts.

Time‑Slice (Time‑Slot) Design

Microcontrollers often need to handle several periodic tasks (LED refresh, seven‑segment scanning, key debounce) simultaneously. A single blocking loop cannot serve them all. The solution is to use a high‑frequency RTC interrupt (e.g., every 125 µs) as a base tick and derive multiple software timers (2 ms, 5 ms, 500 ms, etc.). Each timer decrements on every tick and sets a flag when it expires.

Implementation Steps

Configure the RTC to generate an interrupt every 125 µs.

In the ISR, decrement a set of counter registers (e.g., ref_2ms, ref_5ms, ref_500ms) and set corresponding flags when they reach zero.

In the main loop, call a TimeService() routine that checks the flags and executes the associated tasks (key debounce, display refresh, etc.).

Design the program so that it “runs while waiting” – the ISR only updates counters, and the main loop continues processing other work.

Sample ISR and Service Routine

void RTC_ISR(void) {
    // 125 µs base tick
    if (--ref_2ms == 0) { flag_2ms = 1; ref_2ms = 16; }
    if (--ref_5ms == 0) { flag_5ms = 1; ref_5ms = 40; }
    if (--ref_500ms == 0) { flag_500ms = 1; ref_500ms = 4000; }
}

void TimeService(void) {
    if (flag_2ms) { flag_2ms = 0; /* handle 2 ms tasks */ }
    if (flag_5ms) { flag_5ms = 0; /* handle 5 ms tasks */ }
    if (flag_500ms) { flag_500ms = 0; /* handle 500 ms tasks */ }
}

This approach allows dozens of independent timers to run concurrently with negligible overhead, avoiding the classic “dead‑loop waiting” problem.

Benefits and Caveats

Highly portable: only the hardware‑layer code needs modification for a new board.

Scalable: adding more timers only requires extra counter variables.

Responsive: the main loop never blocks on a single delay, so other tasks keep running.

Limitations: the method assumes the ISR is short (a few microseconds) and that timer resolution (125 µs) meets the application’s timing requirements.

Conclusion

Combining layered architecture with a time‑slice design yields clean, reusable, and efficient microcontroller code. By isolating hardware specifics, providing a uniform driver interface, and using a single high‑frequency interrupt to drive multiple software timers, developers can handle complex, concurrent tasks without resorting to busy‑wait loops.