Sub‑10 ms Phase‑Change Memristor Chip Accelerates Brain Cortex Reconstruction by 480×

Neural dynamical systems (NDS) embed neural networks into continuous‑time differential equation solvers, offering high accuracy for tasks such as three‑dimensional brain‑cortex surface reconstruction, but each iteration requires adaptive step‑size search and repeated neural network evaluation, leading to latencies of hundreds of milliseconds on GPUs, FPGAs or ASICs.

The authors identify three hardware bottlenecks: (1) the adaptive step‑size search consumes roughly one‑third of chip area and one‑fifth of latency; (2) the embedded neural network (ENN) incurs over 25 % of total delay due to frequent inference and data movement; (3) special kernels such as square‑root calculations suffer from the von Neumann memory wall.

To address the first bottleneck, the team exploits the controlled conductance drift (CCD) of phase‑change memory (PCM) devices. By encoding the step size Δt directly in the drifting conductance of a GST‑based memristor, the physical drift replaces the digital search, eliminating the need for extensive read/write and multiplication circuitry. Experiments show repeatable drift across SET and RESET states and endurance of >10¹⁰ cycles, indicating multi‑year stable operation.

For the ENN computation, a compute‑in‑memory (CIM) approach is adopted. The PCM’s multi‑level cell (MLC) capability stores neural weights as discrete conductance levels (8 levels representing ±10, ±15, ±25, ±35, ±45 S). A differential 1T1R array of 288 × 512 cells (≈147 k devices) implements high‑precision write‑verify programming, enabling on‑chip matrix‑multiply‑accumulate without moving data to separate arithmetic units.

The fabricated 40 nm NDS chip runs at a 50 MHz clock and integrates the drift‑based step‑size generator, SAR‑ADC, and word/bit/selection line drivers. Compared with a CMOS‑based ASIC, the PCM‑based design saves 0.26 mm² area and removes multiplier and buffer blocks, yielding a total die area of 0.28 mm². Performance measurements on the same ENN and step‑size tasks show speedups of 3.82–36.27× and power reductions of 11.75–24.73×.

In a high‑fidelity cortical reconstruction benchmark (white‑matter and gray‑matter surface generation), the PCM‑NDS chip completes a full reconstruction in 3.85 ms to 426.31 ms, a 50.38–478.18× acceleration over GPU A100. Accuracy metrics (average symmetric surface distance and Hausdorff distance) meet high‑fidelity requirements, and self‑intersection rates are markedly lower than those of traditional FreeSurfer or plain neural‑network pipelines.

The work demonstrates that a physical property once considered a defect—conductance drift—can be harnessed as a natural computational resource, enabling ultra‑low‑latency NDS hardware. This paradigm suggests broader opportunities for memristor‑based analog computation beyond deep‑learning matrix multiplication, potentially shaping the next generation of low‑delay AI accelerators for digital twins, medical imaging, and embodied intelligence.