Superscalar vs Superpipeline: The Hidden Tricks Accelerating CPUs

1. Superscalar Pipeline: Parallel Execution

What is superscalar?

Normal pipeline: 1 ALU, 1 pipeline → at most 1 instruction per cycle
Superscalar: multiple ALUs, multiple pipelines → at most several instructions per cycle
Analogy:
- Normal pipeline = 1 chef, 1 line
- Superscalar = 4 chefs, 4 lines cooking 4 dishes simultaneously

Superscalar structure diagram

┌────────────────────────────────────────────┐
│          Instruction Issue Unit            │
│   (issues multiple instructions per cycle) │
└──────────────────┬───────────────────────────┘
          │       ┌──────────┼──────────┐
          ↓       ↓          ↓          ↓
        ┌─────┐ ┌─────┐ ┌─────┐
        │ ALU │ │ ALU │ │ MUL │
        └─────┘ └─────┘ └─────┘
          │       │       │
          ↓       ↓       ↓
        ┌─────┐ ┌─────┐ ┌─────┐
        │Pipe1│ │Pipe2│ │Pipe3│
        └─────┘ └─────┘ └─────┘
          │       │
          └───────┼───────┘
                  ↓
            ┌───────────────┐
            │ Register Write‑Back │
            └───────────────┘

Issue width (measure of superscalar)

Superscalar metric: Issue Width
- 2‑issue: up to 2 instructions per cycle
- 4‑issue: up to 4 instructions per cycle
- 8‑issue: up to 8 instructions per cycle
Common configurations:
- Intel Pentium: 2‑issue
- Intel i7: 4‑issue
- Apple M1: 8‑issue

Challenges of superscalar design

Challenges
1. Instruction scheduling – need to find independent instructions; handled by compiler or hardware; requires complex dependency analysis
2. Resource conflicts – multiple ALUs may contend for the same resource
3. Branch prediction – misprediction penalty is larger because multiple pipelines must be flushed

2. Superpipeline: Deeper Stages

What is a superpipeline?

Normal pipeline: 5 stages
Superpipeline: 10, 15, 20 or more stages
More stages → shorter clock period → higher clock frequency
Analogy:
- Normal pipeline: finish a dish in 90 seconds
- Superpipeline: finish half a dish in 45 seconds, but with more steps

Superpipeline structure

Normal 5‑stage pipeline: IF → ID → EX → MEM → WB
Super 10‑stage pipeline: IF1 → IF2 → ID1 → ID2 → EX1 → EX2 → MEM1 → MEM2 → WB1 → WB2
Each stage is simpler, clock period shorter, frequency higher

Pros and cons of superpipeline

Advantages
- Higher clock frequency
- Per‑instruction latency unchanged (still 5 cycles)
- Deeper pipeline depth
Disadvantages
- Per‑instruction latency unchanged (still 5 steps)
- More total cycles
- Branch misprediction penalty larger
- More pipeline stages increase stall impact

3. Comparison: Superscalar vs Superpipeline

Core idea : Superscalar – multiple pipelines in parallel; Superpipeline – more pipeline stages.

Goal : Superscalar – more instructions per cycle; Superpipeline – higher clock frequency.

Complexity : Superscalar – complex instruction scheduling; Superpipeline – tight timing.

Power consumption : Both tend to increase power.

Typical examples : Superscalar – Intel Pentium; Superpipeline – early RISC designs.

4. Modern CPUs: Combining Both Techniques

Modern high‑end CPU = Superscalar + Superpipeline
Example: Intel Skylake
- 4‑issue superscalar
- 14‑stage pipeline
- Up to 4 instructions per cycle
Benefits: high frequency and high parallelism
Costs: exploding design complexity, power, and heat

5. Pipeline Depth Evolution

Evolution history
1989: Pentium → 2‑issue superscalar
1993: Pentium Pro → out‑of‑order + superscalar
1999: Pentium III → 10‑stage pipeline
2000: Pentium 4 → 31‑stage pipeline (NetBurst)
2006: Core 2 → 14‑stage pipeline
2015: Skylake → 14‑19‑stage pipeline
Lessons:
- Deeper pipelines are not always better
- Excess depth leads to power explosion, heat explosion, and high branch‑misprediction cost
Conclusion: Modern CPUs seek a balance rather than extremes

6. IPC (Instructions Per Cycle)

IPC = Instructions Per Cycle = number of instructions executed each cycle
IPC is a key metric of CPU efficiency.
Factors affecting IPC:
1. Superscalar issue width
2. Pipeline efficiency
3. Branch prediction accuracy
4. Cache hit rate
Performance = IPC × clock frequency

7. Power Cost of Higher Frequency

Power formula: P = C × V² × f
where C = capacitance load, V = voltage, f = frequency
Doubling frequency roughly doubles power (if other factors unchanged)
Increasing voltage raises power quadratically
Consequences:
- Laptops throttle frequency
- Servers prefer many cores over high single‑core frequency
- Power wall is more limiting than frequency wall

8. Out‑of‑Order Execution: Superscalar’s Partner

Superscalar needs to solve:
- Instruction order
- Data dependencies
- Execution efficiency
Out‑of‑Order execution (OoO):
- Executes instructions non‑sequentially as long as results are correct
- Maximizes pipeline utilization
Sequential execution example:
Instr1 → Instr2 → Instr3 (each takes 10 cycles, total 30 cycles)
Out‑of‑Order example:
Instr1 and Instr2 execute in parallel, Instr3 follows when ready, reducing total time

9. Summary: Two Paths to Faster CPUs

Superscalar: horizontal scaling – add more pipelines, execute more instructions per cycle, complexity lies in scheduling.
Superpipeline: vertical scaling – add more pipeline stages, increase frequency, complexity lies in timing.
Modern CPUs adopt both:
- Superscalar width 4‑8
- Pipeline depth 14‑20
- Out‑of‑Order execution
- Multi‑core designs
These combined techniques explain the strong performance of today’s processors.

Core takeaways:

Superscalar – multiple pipelines in parallel, multiple instructions per cycle.

Superpipeline – more pipeline stages, higher frequency.

Both can be combined for parallelism and high frequency.

Modern CPUs use superscalar, deep pipelines, out‑of‑order execution, and many cores.

Performance = IPC × clock frequency; optimization must balance both dimensions.