Understanding Intel CPU Naming Rules, Generations, and Microarchitecture (i5-7200U Example)

Hello everyone, I'm Fei! On October 16 Intel launched the 14th‑generation Core processors, and many people find the model numbers confusing. Using my old ThinkPad x270 with an Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz 2.71 GHz , I explain the naming rules, generation codes, and hardware details.

1. Intel CPU Naming Rules

Intel splits a CPU model into five parts: brand mark, brand modifier, generation number, SKU, and product‑line suffix. The brand mark distinguishes families such as Core, Celeron, Pentium, Xeon, and Atom. The brand modifier (i3, i5, i7, i9) indicates market positioning from low‑end to high‑end.

The generation number (e.g., "7" in i5‑7200U) corresponds to the internal code name (Kaby Lake for the 7th generation) and roughly indicates the release year and performance level.

The SKU is an internal inventory identifier, and the suffix (U, H, X, K, etc.) denotes power/performance characteristics (U = low‑power, H = high‑performance, K = unlocked).

Examples: Intel(R) Core(TM) i5-7200U CPU means a Core series, i5 tier, 7th‑gen Kaby Lake, SKU 200, low‑power U suffix. Newer models like Intel(R) Core(TM) i9-14900K , i7-14700K , i5-14600K follow the same pattern, with generation 14 and different SKUs.

2. CPU Generations

Each generation has a release year, process node, and micro‑architecture. The table below summarizes generations from the 4th (Haswell, 22 nm) to the 14th (Raptor Lake Refresh, 7 nm):

Year

Generation

Code Name

Process

Micro‑architecture

2013

4th

Haswell

22 nm

Haswell

2014

5th

Broadwell

14 nm

Haswell

2015

6th

Skylake (client)

14 nm

Skylake

2016

7th

Kaby Lake

14 nm

Skylake

2017

8th

Coffee Lake

14 nm

Skylake

2018

9th

Coffee Lake Refresh

14 nm

Skylake

2019

10th

Ice Lake (client)

10 nm

Sunny Cove

2020

11th

Tiger Lake

10 nm

Willow Cove

2021

12th

Alder Lake S

7 nm

Golden Cove / Gracemont

2022

13th

Raptor Lake

7 nm

Raptor Cove / Gracemont

2023

14th

Raptor Lake Refresh

7 nm

Raptor Cove / Gracemont

The i5‑7200U is a 7th‑gen Kaby Lake part built on a 14 nm process. Its die diagram shows a dual‑core, four‑thread layout with integrated graphics (Gen9.5), a memory controller supporting DDR4‑2400, two physical cores, L3 cache, and a System Agent handling PCIe lanes and an Image Processing Unit.

3. Physical Core Micro‑architecture Design

Each core consists of three main blocks:

Front End (yellow) : fetches instructions from memory, decodes them, performs branch prediction, and fills the instruction queue. It includes a 32 KiB L1 instruction cache and an instruction TLB.

Execution Engine / Back End (green) : executes decoded micro‑operations using eight ports (Port0‑Port7). Ports 0,1,5,6 handle integer/floating‑point adds; Ports 2,3 handle address generation and loads; Port 4 handles stores. Up to eight µops can be processed per clock cycle.

Memory Subsystem (purple) : provides L1 data cache (32 KiB), L2 cache (256 KiB), and a data TLB, all residing on‑chip for faster access than main memory.

Different generations modify these blocks, affecting single‑core performance.

Summary

Using the i5‑7200U as a case study, we covered Intel's CPU naming scheme, how to decode a model string, the evolution of generations from Haswell to Raptor Lake Refresh, and the internal layout of a Kaby Lake core, including front‑end, back‑end, and memory subsystems. Understanding these details helps developers quickly assess a processor's capabilities and anticipate architectural differences across generations.