Understanding LCD Hardware: Pixel Formats, Framebuffer, and Interface Standards

Different LCD Hardware Operation Principles

1. Application‑engineer view

LCD screen is a matrix of pixels: each row contains xres pixels and there are yres rows, giving a resolution of xres × yres. Controlling the colour of each pixel renders text and images.

1.1 Pixel colour representation

Colours are expressed as red, green and blue components. Common bits‑per‑pixel (bpp) formats: bpp – number of bits used for each pixel. 24bpp – stored in 32 bits (8 bits unused); 8 bits each for R, G, B. 16bpp – examples: rgb565 (5 R 6 G 5 B) and rgb555 (5 R 5 G 5 B, 1 unused).

1.2 Sending colour data to the LCD

If each pixel uses 16 bits, the framebuffer size is xres × yres × 16 / 8 bytes. The framebuffer is a contiguous memory region where each entry corresponds to one pixel and matches the pixel colour format. After the LCD controller is configured, writing colour values into the framebuffer updates the display.

One framebuffer entry per pixel.

Entry size matches the colour format (e.g., 16 bits, 24 bits).

Writing to the framebuffer drives the screen.

2. Driver‑engineer view

2.1 Unified LCD hardware model

2.2 MCU‑typical 8080‑interface LCD module

Low‑performance microcontrollers often use an external module that integrates a SRAM framebuffer, an LCD controller, and the display panel. The MCU‑module interface includes:

CS (chip‑select)

RD (read)

WR (write)

Data bus

CMD/DATA line to distinguish command from data transfers.

The SRAM framebuffer limits maximum screen size because SRAM is costly.

2.3 MPU‑typical TFT‑RGB interface

Embedded Linux systems usually employ a TFT‑RGB interface where the memory controller and LCD controller are integrated in the SoC and an external LCD panel is attached. Key signals:

DCLK – pixel clock.

HSYNC – horizontal sync (line start).

VSYNC – vertical sync (frame start).

RGB data lines.

DE – data enable.

1、Horizontal pixel shift: DCLK
2、Line start from rightmost to leftmost of next line: HSYNC
3、Frame start from bottom‑right to top‑left: VSYNC
4、RGB – data lines
5、DE – data enable

2.4 MIPI standard

MIPI (Mobile Industry Processor Interface) is an open standard defined by the MIPI Alliance to standardise internal mobile interfaces such as display, camera and RF modules.

For LCDs, MIPI defines three families:

MIPI‑DBI (Display Bus Interface)

Supports both data and command transmission; classic 8080‑type bus belongs here.

Type B: parallel bus (8/9/16/18/24 bits).

Type C: serial (3‑ or 4‑line SPI).

MIPI‑DPI (Display Pixel Interface)

Pixel‑level control used by MPU‑integrated LCD controllers.

Supports 24 bits/pixel (8 R 8 G 8 B), 18 bits/pixel (6 R 6 G 6 B), and 16 bits/pixel (5‑6‑5).

MIPI‑DSI (Display Serial Interface)

Serial interface that reduces pin count compared with DBI/DPI.

One data lane up to 500 Mbps.

DSI version 1.01, D‑PHY version 1.00.

Reference: https://www.zhihu.com/question/22263252/answer/410201820