Understanding PCIe: History, Architecture, and Link Initialization

1. Origin of PCIe

PCIe (Peripheral Component Interconnect Express) was originally called “3GIO” by Intel in 2001 and officially introduced in 2003 to replace the parallel PCI, PCI‑X and AGP buses. It uses packet‑based communication across transaction, data link, and physical layers.

2. Common PCIe Devices

PCIe employs a tree topology consisting of Root Complexes, Repeaters (Retimers or Redrivers), and Endpoints such as SSDs, network cards, and graphics cards.

3. Link Initialization

During initialization, devices detect each other, perform receiver detection, and start serial transmission at 2.5 GT/s (PCIe 1.0 speed). Control signals such as PERST#, WAKE#, CLKREQ#, and REFCLK# manage reset, power‑state transitions, and provide the 100 MHz reference clock required for data transfer.

After detection, the link undergoes training, configuration, and calibration of lane width, rate, polarity, and other parameters before entering the active L0 state.

4. Link Equalization

For PCIe generations 3 and above, additional link equalization phases (Phase 0, Phase 1, Phase 2, Phase 3) adjust Tx and Rx presets to optimize signal quality and achieve target bit‑error‑rates (BER ≤ 10⁻⁴, then ≤ 10⁻¹²). Each phase involves negotiation between upstream and downstream ports, with preset values defining pre‑emphasis and de‑emphasis settings.

Multiple equalization cycles may be required for higher‑speed generations (e.g., Gen5 may need three equalization steps). When equalization completes, the link operates at the negotiated speed (e.g., Gen3 at 8 GT/s) in the L0 state.

In designs with long trace lengths, additional signal‑conditioning devices such as Retimers or Redrivers are used to maintain signal integrity between the Root Complex and endpoints.