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Alibaba Cloud announced that two of its server‑R&D papers were selected for DesignCon and ECTC 2024, presenting measurement‑based studies on PCIe 5.0/6.0 link performance under air and immersion cooling and a long‑term reliability analysis of crystal oscillators in various immersion‑cooling fluids, insights that guide next‑generation server architecture and large‑scale liquid‑cool deployment.
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This article provides a comprehensive overview of the PCIe interface evolution, detailing the specifications, version milestones, bandwidth improvements, encoding and signaling changes from PCIe 3.0 through PCIe 7.0, and their impact on data‑center, AI/ML, and consumer hardware.
This article explains the main components of PCIe architecture—including Root Complex (RC), switches, and PCIe‑to‑PCI bridges—how they are implemented in different processor systems such as x86 and PowerPC, and the mechanisms for QoS, port arbitration, and extended configuration space.
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This article provides a comprehensive technical overview of the NVMe (Non‑Volatile Memory Express) specification, covering its logical device interface, namespace concepts, queue structures, PCIe register layout, command formats, controller initialization, interrupt handling, and data protection mechanisms.
The article explains how the adoption of flash storage, the limitations of legacy SCSI protocols, and the emergence of PCIe‑based NVMe and NVMe‑oF have transformed data‑center architectures, delivering higher throughput, lower latency, and better support for demanding database and memory‑intensive workloads.
This article introduces the high‑performance NVMe storage protocol, its architecture, advantages over traditional SATA/SAS, the evolution of NVMe‑oF with RDMA and Fibre Channel, and provides links to related technical resources and download materials.
The article explains GPU evolution, its integration with CPUs, interconnect technologies like PCIe and NVLink, market shares of NVIDIA, AMD and Intel, AI accelerator types (GPU, FPGA, ASIC), and the roles of training and inference in cloud AI, while also promoting a paid 182‑page PPT resource.
This article explains how a host discovers and configures PCIe devices through a depth‑first enumeration process, describes the BDF addressing scheme, and illustrates memory‑mapped I/O interactions such as NVMe command submission using Linux lspci commands.