Unlocking Memory Secrets: Why Random IO Slows Down and How to Optimize It

Part 1: Physical Aspects

The first three articles explain the hardware fundamentals of memory:

Understanding Memory Alignment Fundamentals – Uses the familiar concept of memory alignment to illustrate how memory modules are physically built and how they interact with the bus to transfer data to the CPU.

Random vs. Sequential Memory I/O Speed – Shows that, contrary to common belief, random memory accesses are 3–4 times slower than sequential accesses, based on measured latency.

From DDR to DDR4: Frequency Limits – Clarifies why newer DDR generations do not dramatically increase core frequency, describing prefetch limitations, non‑continuous data storage, and bank‑group effects that prevent reaching advertised speeds.

Part 2: Hands‑On Tests

After grasping the theory, three practical experiments were performed:

Sequential vs. Random I/O Latency Test – Measured memory latency under various conditions; the fastest path is actually the CPU cache, while sequential I/O averages ~10 ns and random I/O is about four times slower.

Real Bandwidth vs. Manufacturer Claims – Tested a memory module advertised at 8.5 GB/s; under worst‑case conditions the observed bandwidth dropped to only 474 MB/s, highlighting the impact of CL, tRCD, tRP delays and QPI bus overhead.

NUMA Architecture Latency Differences – Demonstrated that memory accesses within the same NUMA node are faster than cross‑node accesses, which must travel the QPI bus and incur additional latency.

Part 3: Practical Applications

Finally, three real‑world use cases show why deep hardware knowledge matters for developers:

PHP 7 Memory Performance Optimizations – Examines kernel data‑structure tweaks that save a few bytes but yield large performance gains when the CPU‑memory interaction is understood.

Turning Random I/O into Sequential I/O – Describes a project that reorganizes memory access patterns to keep the memory subsystem in its most efficient state, achieving multiple‑fold speed improvements.

Redis Single‑Instance Memory Limit and NUMA Trap – Explores how a single Redis process can hit memory limits on NUMA systems and what pitfalls developers should avoid.

The author concludes the memory series and promises upcoming articles on storage and networking, wishing readers a happy 2020.