What Nvidia’s B100 and GB200 Reveal About the Future of AI GPUs
The GTC 2024 recap highlights Nvidia’s upcoming B100 and GB200 GPUs, their BlackWell architecture, performance breakthroughs, embodied‑intelligence initiatives, and the expanding AI application ecosystem across industries, offering a clear view of the next wave in accelerated computing.
GTC 2024, held at the San Jose Convention Center and online, showcased breakthrough results in accelerated computing, generative AI, and robotics, positioning Nvidia at the forefront of the AI hardware landscape.
B100 and subsequent chip roadmap : The B100 is expected to adopt the new BlackWell architecture, delivering roughly double the performance of the H200 series and up to four times the H100. It will be the first Nvidia chip built with a multi‑chiplet (MCM) design, likely using TSMC N3 or N4P processes and CoWoS‑L packaging. Initial memory may be 200 GB HBM3e, with 224 SerDes links. Early versions will use PCIe 5.0 and C2C connections, consuming about 700 W and fitting existing HGX servers; a later 1000 W, liquid‑cooled variant is planned, and ConnectX8 will enable a full 800 Gbps GPU‑to‑GPU network. The GB200 is slated for 2024‑2025, featuring CPU‑GPU NVLink‑C2C links, possibly NVLink 5.0 and 192 GB HBM3e, promising further performance gains.
Embodied intelligence : Nvidia’s robotics track featured companies such as Agility Robotics, Boston Dynamics, Disney, and Google DeepMind, displaying 25 robots. CEO Jensen Huang emphasized embodied AI as the next wave. Early 2024 saw Nvidia invest in humanoid‑robot startup FigureAI and launch the General Embodied AI Research (GEAR) lab, indicating a strategic push in this area.
AI applications : Over 1,000 companies and 300 exhibitors demonstrated Nvidia’s platform across agriculture, automotive, cloud services, and more. Multimodal large models are driving higher inference compute and bandwidth demands, which will benefit data centers and CDNs with a new surge of traffic.
Performance expectations : Nvidia projects the B100 to achieve at least twice the performance of the H200 and four times that of the H100, with memory bandwidth and capacity significantly increased. The chip’s design aims to shorten the iteration cycle to one year, accelerating ecosystem upgrades.
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