Why 1.6 Tbps Ethernet Is the Next Frontier for Data Centers

Since the 1980s Ethernet has evolved from 10 Mbps coaxial links to today’s 100 Gbps and 400 Gbps deployments, and the industry is now pushing toward a 1.6 Tbps (1600 Gbps) standard to meet the exploding bandwidth demands of modern data centers, high‑performance computing, and processor‑to‑processor communication.

Why Such High Speed Is Needed

Two main drivers are identified: (1) the need to move and store massive volumes of data faster, and (2) the requirement for predictable, ultra‑reliable networking even for the most demanding control‑system workloads.

Early Adoption: Processor‑to‑Processor Communication

When multiple chips are linked together, the aggregate compute capability can be dramatically increased, but the inter‑chip link quickly becomes the bottleneck. 1.6 Tbps Ethernet offers terabit‑per‑second throughput with sub‑microsecond latency, enabling direct processor‑to‑processor links and future switch‑to‑switch back‑plane connections.

IEEE 802.3dj Standardization

The IEEE 802.3dj working group defines the physical‑layer and management parameters for 200 G, 400 G, 800 G, and 1.6 T operation. Key requirements include a MAC‑layer bit‑error‑rate (BER) of 10⁻¹³, optional 8‑ or 16‑lane AUI interfaces using 112 G or 224 G SerDes, and the following physical‑layer specifications:

Eight twisted‑pair copper cables, ≥1 m reach per direction.

Eight multimode fiber pairs, up to 500 m.

Eight single‑mode fiber pairs, up to 2 km.

The baseline functionality is expected to be frozen by spring 2026, with a draft ready by the end of 2024.

1.6 Tbps Ethernet Subsystem Overview

The subsystem consists of the network application layer, queues, the Ethernet controller (MAC + PCS), optional AUI attachments, and the physical media (copper, fiber, or back‑plane). The controller typically integrates a MAC and a PCS; the PCS handles encoding, while the MAC manages framing, address handling, and FCS verification.

MAC Variants

NIC MAC : Embedded in network interface cards of servers, routers, or workstations. It adds/removes Ethernet headers, checks the frame‑check‑sequence (FCS), and forwards payloads (typically IP packets).

Switch/Bridge MAC : Implemented inside Ethernet switches or bridges. Each port contains a dedicated MAC that forwards frames and collects RMON statistics. Speed adaptation occurs above the MAC in the queueing logic.

Coding and RS‑FEC

For lower‑speed Ethernet, the PCS performs simple encoding. At 1.6 Tbps the PCS incorporates Reed‑Solomon forward‑error‑correction (RS‑FEC). Each codeword consists of 514 × 10‑bit symbols expanded to 544 symbols, incurring a 6 % overhead. The FEC is distributed across the eight physical lanes, allowing parallel decoding and reducing latency.

Physical Layer: PAM‑4 and SerDes

The 1.6 Tbps link uses four‑level pulse‑amplitude modulation (PAM‑4), encoding two bits per symbol and effectively doubling bandwidth compared with NRZ. Eight lanes run at 212 Gbps each, requiring 224 Gbps SerDes to accommodate the 6 % FEC overhead.

Latency Analysis

End‑to‑end latency comprises queueing, processing, transmission, media traversal, and reception phases. For a minimal Ethernet frame, transmission time at 1.6 Tbps is ~0.4 ns (≈2.5 GHz clock). Standard maximum‑size frames take ~8 ns; jumbo frames up to ~48 ns. Fiber adds ~5 ns/m, copper ~4 ns/m. The dominant latency source in the receiver is the RS‑FEC decoder, which must buffer four codewords (12.8 ns) and perform error‑correction, adding additional nanoseconds.

Conclusion

1.6 Tbps Ethernet satisfies the most bandwidth‑intensive and latency‑sensitive workloads. Achieving this speed relies on 224 Gbps SerDes, PAM‑4 signaling, and robust RS‑FEC. Controller latency remains a critical design factor; careful digital design and integration of MAC, PCS, and PHY are essential to meet the 10⁻¹³ BER target while keeping overall latency low.