Why Optical Computing Could Break the AI Power Wall – A Deep Dive

This article systematically reviews the development background, core technologies, industry challenges, and practical progress of optical computing, highlighting its strategic value as a new post‑Moore computing paradigm for AI workloads.

1. Background of Optical Computing Development

1. National strategic focus and local coordination

National level: Optical computing is listed as a major scientific direction in the 14th Five‑Year Plan, with silicon photonics, optical neural networks, and photonic‑electronic AI chips receiving top‑level support.

Local policies: Guangdong, Beijing, Chongqing and other regions have issued action plans that focus on photonic chip R&D and intelligent computing center construction.

2. Traditional electronic computing bottlenecks and optical computing as a key solution

AI demand explosion: Large models such as GPT‑4 drive a surge in intelligent compute, with China’s AI compute capacity reaching 725.3 EFLOPS in 2024 and projected to exceed 1 EFLOPS in 2025.

Electronic bottlenecks: Moore’s law slowdown and high data‑center power consumption create a wall for further scaling.

Optical advantage: Photons offer high bandwidth, low energy consumption, and massive parallelism, giving optical matrix operations 10‑100× the energy efficiency of GPUs.

3. Industry landscape: domestic and overseas progress

Overseas leaders: Lightmatter (MIT technology, $400 M series‑D funding) and Luminous Computing (Princeton technology, $105 M series‑A) focus on photonic‑electronic AI training platforms.

Domestic companies: Shanghai Xizhi Technology (2025 “Tianshu” photonic‑electronic card, 128×128 matrix, $1.5 B C‑round), Suzhou Guangbenwei Technology (first 128×128 phase‑change photonic chip), Beijing XinSuan Technology (high‑dimensional photonic chip prototypes).

Research institutions: Tsinghua University’s “Taiji” chips (160 TOPS/W, Nature publication) and Shanghai Institute of Optics & Fine Mechanics “Meteor‑1” chip (2560 TOPS, >100‑way parallelism).

2. Core Technologies: Definition, Architecture, and Roadmap

1. Definition and classification

Definition: Optical computing uses photons as information carriers, leveraging modulation, interference, and diffraction to perform computation, aiming to overcome speed, power, and bandwidth limits of electronic processors.

Classification:

Photonic quantum computing – exploits superposition and entanglement, still exploratory.

Photonic classical computing – includes digital optical logic and analog optical processing; integrated photonic platforms for analog computing are the current research hotspot.

2. Overall technical architecture

The optical computing stack consists of four layers that jointly support the full workflow from hardware to applications.

Architecture Layer

Core Content

Current Progress

Hardware layer

Optical materials (silicon, lithium niobate), core devices (MZI arrays, MRR arrays, photodetectors), integrated compute units.

128×128 optical matrix arrays demonstrated; silicon‑photonic and lithium‑niobate heterogeneous integration mature, wafer‑level yield still under verification.

Basic software layer

Algorithm mapping, calibration scheduling, fault‑tolerance analysis, performance‑optimization tools.

Vendor‑specific toolchains exist, but lack unified standards and interface compatibility.

Model algorithm layer

Optical‑friendly neural networks (O‑CNN/O‑RNN/O‑DNN) that translate AI tasks into optically executable operations.

Feed‑forward networks validated; large models such as Transformers require dedicated optimization for optical execution.

Application layer

Model training/inference, image detection, autonomous driving, biomedicine, etc.

Prototype optical acceleration cards released for research and niche scenarios; large‑scale commercial deployment pending.

3. Core technology routes: four paths for optical matrix computation

Optical matrix multiplication, the core of AI neural networks, can be realized through several competing approaches.

Technology Route

Principle

Advantages

Challenges

Representative Applications

MZI array

Mach‑Zehnder interferometer cascades implement unitary matrix operations via phase tuning.

Supports complex‑valued computation, mature process, high community acceptance.

Phase error accumulation and on‑chip attenuation increase with cascade depth.

General AI inference, signal processing.

MRR array

Micro‑ring resonators map matrix elements through wavelength‑division multiplexing; parallel computation across wavelengths.

Compact size, simple matrix mapping.

Limited channel count, temperature sensitivity.

Low‑power small‑scale inference.

PCM structure

Phase‑change materials (e.g., Ge₂Sb₂Te₅) switch between crystalline and amorphous states to store weights and modulate optical paths.

In‑memory compute, low power, small footprint.

CMOS incompatibility, slower modulation latency.

Edge‑AI tasks with stringent power budgets.

Sub‑wavelength diffraction structure

Metasurfaces engineer diffraction coefficients as neural weights; cascaded diffraction performs computation.

Precise wave‑front control, supports complex operations.

Nanofabrication complexity, stability issues.

High‑accuracy image recognition.

4. System architecture: hybrid photonic‑electronic is mainstream, all‑optical remains experimental

Hybrid architecture: Light performs linear matrix multiplication, while electronics handle nonlinear activation, pooling, and control logic, balancing performance and flexibility.

Process flow: Electrical signal modulates light → optical linear compute (MZI/MRR) → photo‑detection → electronic nonlinear processing → result output.

Advantages: Avoids the bottleneck of fully optical nonlinear devices, achieving high efficiency with practical programmability; adopted by Xizhi and Lightmatter.

All‑optical architecture (lab stage): Aims for fully optical linear + nonlinear computation for maximal energy efficiency, but suffers from large, power‑hungry nonlinear devices and integration challenges.

3. Challenges and Recommendations

1. Materials and devices: fundamental capabilities need improvement

Challenges: High loss in silicon waveguides, difficult laser integration, environmental instability, and limited nonlinear device performance.

Recommendations: Develop low‑loss waveguide materials, build long‑term stability test platforms, and create new modulators and light sources such as VCSELs.

2. Integration and packaging: scaling bottlenecks

Challenges: Incompatible multi‑material integration (III‑V lasers, lithium‑niobate modulators, germanium‑silicon detectors), waveguide crosstalk, and lack of unified packaging standards.

Recommendations: Advance photonic‑electronic co‑packaging (CPO), define standard interfaces, and optimize waveguide layout to reduce crosstalk.

3. Hybrid system efficiency: co‑optimization needed

Challenges: Limited precision of optical linear compute (≈8 bit), matrix size constraints, optical‑electronic conversion latency and loss, and sub‑optimal task partitioning.

Recommendations: Implement real‑time phase calibration (e.g., FPGA‑based compensation), allocate dense linear tasks to the optical domain and nonlinear tasks to electronics, and improve photodetector performance.

4. Software‑hardware co‑design: toolchain and algorithm gaps

Challenges: EDA tools lack photonic simulation modules, AI models (e.g., Transformers) are not adapted to optical characteristics, and error‑compensation algorithms cannot handle complex physical noise.

Recommendations: Build dedicated photonic EDA and compilers, create open‑source software platforms for the community, and develop advanced error‑compensation techniques using machine‑learning prediction.

4. Industry Innovation Practice

1. Enterprise cases

Xizhi Technology: 2025 “Tianshu” photonic‑electronic compute card with >40 000 photonic devices, 128×128 matrix, 4 TOPS/W, runs ResNet‑50 and Qwen‑7B models.

Guangbenwei Technology: World’s first 128×128 phase‑change photonic chip (2024), in‑memory compute design targeting thousand‑TOPS scale.

Lightmatter (USA): “Envise” photonic chip delivering 25 TOPS peak performance at 5 TOPS/W, based on MZI arrays, collaborating with cloud providers for large‑scale deployment.

2. Research institution cases

Tsinghua University – “Taiji” series: Achieves 160 TOPS/W; “Taiji‑II” enables full forward training without back‑propagation, breaking large‑scale optical neural network limits.

Shanghai Institute of Optics & Fine Mechanics – “Meteor‑1”: Over 100‑way parallelism, 2560 TOPS peak compute via wavelength‑division multiplexing, offering two orders of magnitude higher energy efficiency than conventional photonic approaches.

5. Conclusion

Optical computing, with its high energy efficiency and massive parallelism, is poised to break the power and performance walls of traditional electronic processors. Supported by policy, advancing core technologies such as mature MZI arrays, and demonstrated by leading enterprises and research labs, photonic computing is expected to become a key component of future intelligent‑computing infrastructure within the next 5‑10 years, enabling autonomous, self‑controlled AI compute capabilities.