Why PCIe Performance Falls Short of Its Bandwidth Limits—and How to Optimize It

Data Encoding

PCIe’s evolution from 1.0 to 5.0 has doubled data rates each generation, but the actual efficiency is limited by the encoding scheme used. Early versions (PCIe 1.0/2.0) employ 8b/10b encoding, converting 8 bits of data into 10 bits to balance the number of zeros and ones, which introduces roughly a 20% overhead. Later generations (PCIe 3.0/4.0/5.0) adopt 128b/130b encoding with scrambling, reducing overhead to about 1.5%, while PCIe 6.0 uses PAM4 modulation and a 1b/1b scheme, eliminating encoding loss.

The 8b/10b example shows how a binary pattern is transformed into a balanced 10‑bit symbol, illustrating the inherent 20% bandwidth penalty.

Link and Physical Layer

Data exchange between a host and a PCIe device occurs via Transaction Layer Packets (TLPs) that contain a Header, optional Payload, and optional ECRC. The Header (12 or 16 bytes) carries routing and type information, while the Payload can be up to 4096 bytes of user data. During transmission, the Data Link Layer adds Sequence Numbers and LCRC, and the Physical Layer adds start/end markers (the latter removed from PCIe 3.0 onward). These additional fields consume bandwidth.

Maximum Payload Size (MPS)

MPS defines the largest Payload a TLP may carry, with allowed values of 128 B, 256 B, 512 B, 1 KB, 2 KB, or 4 KB. Larger MPS increases the proportion of useful data per packet but also raises latency, error probability, and overall load. In practice, most systems use 128 B, 256 B, or 512 B. During link initialization, the MPS of all devices (Root Complex, Switch, Endpoint) is negotiated to a common value.

Maximum Read Request Size (MRRS)

MRRS limits the size of a read request to prevent a single request from monopolizing bandwidth. Like MPS, it can be set to 128 B‑4 KB. A low MRRS forces the host to issue many small read TLPs, increasing ACK/NAK overhead. Typically MRRS is equal to or larger than MPS; for example, with MPS = 128 B and MRRS = 512 B, a 512‑byte read is split into four TLPs.

These factors—encoding overhead, link‑layer packet fields, and payload‑size settings—are intrinsic to PCIe and cannot be eliminated, but understanding them helps engineers tune configurations to approach the link’s theoretical performance limits.