Accelerators | BestHub

Architects' Tech Alliance

Jun 22, 2024 · Artificial Intelligence

Rising Compute Demand of Generative AI Models and GPU Accelerator Trends in 2024

The article analyzes how generative AI models from GPT‑1 to the upcoming GPT‑5 are driving exponential growth in compute requirements, prompting massive cloud capital expenditures and intense competition among GPU vendors such as NVIDIA, AMD, Google, and emerging domestic chip makers, while also highlighting interconnect innovations and cost‑effective solutions.

AIAcceleratorsCompute

0 likes · 12 min read

Rising Compute Demand of Generative AI Models and GPU Accelerator Trends in 2024

Architects' Tech Alliance

Mar 7, 2022 · Fundamentals

FPGA Technology for Compute‑Intensive and Communication‑Intensive Tasks: Performance, Deployment, and Market Overview

This article examines how FPGA accelerators handle compute‑intensive and communication‑intensive workloads, compares their performance and latency to CPU and GPU solutions, explores various deployment models in data centers, and outlines the evolving Chinese and global FPGA market landscape.

AcceleratorsFPGAcloud computing

0 likes · 13 min read

FPGA Technology for Compute‑Intensive and Communication‑Intensive Tasks: Performance, Deployment, and Market Overview

Alibaba Cloud Infrastructure

Dec 31, 2017 · Artificial Intelligence

Maximizing Machine Learning Performance with Heterogeneous Computing Resources

At the 2017 International Workshop on Mathematical Issues in Information Sciences, Alibaba researcher Zhang Weifeng presented a talk on leveraging heterogeneous computing—re‑architected processors, memory‑wall mitigation, and integrated software‑hardware optimization—to dramatically improve machine‑learning performance, highlighting the growing importance of compute resources alongside algorithmic advances.

AIAcceleratorsComputer Architecture

0 likes · 5 min read

Maximizing Machine Learning Performance with Heterogeneous Computing Resources

Tencent Architect

Nov 13, 2017 · Artificial Intelligence

Survey of Bandwidth Optimization Techniques in AI Accelerators

This article reviews various architectural strategies—including streaming processing, on‑chip memory optimization, bit‑width compression, sparsity techniques, on‑chip models with chip‑level interconnects, and emerging technologies such as binary networks, memristors, and HBM—to alleviate bandwidth bottlenecks in FPGA/ASIC/TPU AI accelerators.

AIASICAccelerators

0 likes · 20 min read

Survey of Bandwidth Optimization Techniques in AI Accelerators