BestHub
Sign in
Tagged articles
18 articles
Page 1 of 1
Deepin Linux
Deepin Linux
Dec 2, 2025 · Fundamentals

Why CPU Cache Misses Slow Down Your Linux System—and How to Fix Them

CPU caches bridge the speed gap between processors and memory, but cache misses can dramatically degrade performance, especially under high concurrency or big‑data workloads; this article explains cache architecture, common miss causes, diagnostic tools like perf and cachestat, and practical optimization techniques for Linux systems.

CPU cacheLinux performanceMESI Protocol
0 likes · 44 min read
Why CPU Cache Misses Slow Down Your Linux System—and How to Fix Them
Deepin Linux
Deepin Linux
Sep 6, 2025 · Fundamentals

Why Memory Barriers Are Essential for Multithreaded Programming

Memory barriers act like traffic signals for concurrent threads, enforcing a strict order of memory operations to prevent data races, cache incoherence, and compiler reordering, thereby ensuring program correctness and stability across multi‑core and multi‑processor systems.

CPU orderingLinux kernelcache coherence
0 likes · 37 min read
Why Memory Barriers Are Essential for Multithreaded Programming
Deepin Linux
Deepin Linux
Mar 27, 2025 · Fundamentals

Understanding Linux Memory Barriers: Concepts, Types, and Implementation

This article explains why modern multi‑core CPUs need memory barriers, describes the different kinds of barriers (full, read, write), shows how they are implemented in the Linux kernel and hardware, and illustrates their use in multithreaded and cache‑coherent programming.

CPU architecturecache coherenceconcurrency
0 likes · 41 min read
Understanding Linux Memory Barriers: Concepts, Types, and Implementation
Linux Kernel Journey
Linux Kernel Journey
Feb 5, 2025 · Fundamentals

Boost Code Performance by Leveraging CPU Cache Principles

This article explains how CPU caches bridge the speed gap between the processor and main memory, describes cache hierarchy, locality principles, write policies, coherence protocols, and provides concrete C code examples and practical tips such as data alignment and loop restructuring to improve cache hit rates and overall program speed.

CPU cacheMESI ProtocolMemory Hierarchy
0 likes · 30 min read
Boost Code Performance by Leveraging CPU Cache Principles
Deepin Linux
Deepin Linux
Feb 4, 2025 · Fundamentals

Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques

This article explains the fundamental role of CPU cache in bridging the speed gap between processors and memory, covering cache hierarchy, locality principles, write policies, coherence protocols, and practical code optimizations such as data alignment and loop restructuring to improve performance.

CPU cacheData AlignmentMESI Protocol
0 likes · 31 min read
Understanding CPU Cache: Architecture, Hierarchy, and Optimization Techniques
Open Source Linux
Open Source Linux
Jul 7, 2023 · Fundamentals

Why CPUs Need Cache Memory and How the MESI Protocol Ensures Consistency

This article explains the purpose of CPU cache memory, the principles of temporal and spatial locality, the multi‑level cache architecture, the MESI cache‑coherence protocol for multi‑core processors, and the optimizations such as store buffers and memory barriers that address performance and consistency challenges.

CPU cacheMESIMemory Hierarchy
0 likes · 16 min read
Why CPUs Need Cache Memory and How the MESI Protocol Ensures Consistency
Tencent Cloud Developer
Tencent Cloud Developer
Nov 1, 2022 · Fundamentals

Understanding CPU Cache, Memory Hierarchy, and Virtual Memory

The article explains how modern computers use fast SRAM caches (L1‑L3) inside the CPU with various mapping schemes and the MESI coherence protocol to keep data consistent, while DRAM serves as main memory, and virtual memory with multi‑level page tables and a TLB abstracts physical memory, provides isolation, and enables swapping.

CPU cacheMESI ProtocolMemory Hierarchy
0 likes · 16 min read
Understanding CPU Cache, Memory Hierarchy, and Virtual Memory
Xiao Lou's Tech Notes
Xiao Lou's Tech Notes
Jun 22, 2022 · Fundamentals

Why CPU Cache Coherence Matters: From Volatile to MESI and Memory Barriers

This article explores the fundamentals of CPU cache hierarchy, why caches are needed, how cache inconsistency arises in multicore systems, and the mechanisms—such as cache coherence protocols, MESI, store buffers, invalidate queues, and memory barriers—that ensure correct data ordering and visibility across processors.

CPUMESIcache coherence
0 likes · 21 min read
Why CPU Cache Coherence Matters: From Volatile to MESI and Memory Barriers
Top Architect
Top Architect
Feb 1, 2022 · Fundamentals

Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization

This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.

CPU cacheMemory Hierarchycache coherence
0 likes · 21 min read
Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization
21CTO
21CTO
Dec 2, 2021 · Fundamentals

Why Caches Matter: A Deep Dive into CPU Memory Hierarchy and Consistency

This article provides a comprehensive overview of CPU caches, covering why they are needed, their classification, placement and lookup mechanisms, replacement and write policies, and coherence protocols such as MESI, illustrating each concept with diagrams and code examples.

CPUCacheMemory Hierarchy
0 likes · 11 min read
Why Caches Matter: A Deep Dive into CPU Memory Hierarchy and Consistency
Liangxu Linux
Liangxu Linux
Aug 16, 2021 · Fundamentals

Why CPUs Need Cache: A Deep Dive into Cache Mechanics and Coherence

This article explains the motivation behind CPU caches, their classification, placement and lookup methods, replacement and write policies, and coherence protocols, providing a comprehensive overview of cache fundamentals for modern computer architectures.

LRUMemory Hierarchycache coherence
0 likes · 14 min read
Why CPUs Need Cache: A Deep Dive into Cache Mechanics and Coherence