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Top Architect
Top Architect
Feb 1, 2022 · Fundamentals

Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization

This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.

CPU cacheCache CoherencePerformance Optimization
0 likes · 21 min read
Understanding CPU Cache Hierarchy, Cache Coherence, and Performance Optimization
Baidu Geek Talk
Baidu Geek Talk
Apr 21, 2021 · Backend Development

Performance Optimization in Baidu's C++ Backend: Memory Allocation and Access Techniques

Baidu engineers boost C++ backend latency and cost efficiency by eliminating unnecessary string zero‑initialization, using zero‑copy split with SIMD, replacing deep protobuf merges with repeated string fields, employing job‑scoped arenas and custom memory resources for allocation, and applying prefetching, cache‑line awareness, and tuned memory‑order semantics, achieving multiplicative to order‑of‑magnitude speedups.

CMemory AccessMemory Allocation
0 likes · 31 min read
Performance Optimization in Baidu's C++ Backend: Memory Allocation and Access Techniques
vivo Internet Technology
vivo Internet Technology
Mar 10, 2021 · Fundamentals

CPU Performance Optimization Using Top‑Down Micro‑architecture Analysis (TMAM)

The article demonstrates how Top‑down Micro‑architecture Analysis Methodology (TMAM) can quickly pinpoint CPU bottlenecks—such as front‑end, back‑end, and bad speculation stalls—in a simple C++ accumulation loop, and shows that applying targeted compiler, alignment, and branch‑prediction optimizations reduces runtime by roughly 34 % while increasing retiring slots.

CCPU performanceMicroarchitecture
0 likes · 20 min read
CPU Performance Optimization Using Top‑Down Micro‑architecture Analysis (TMAM)
Xiaokun's Architecture Exploration Notes
Xiaokun's Architecture Exploration Notes
Jan 30, 2020 · Fundamentals

How False Sharing Slows Java Programs and How to Eliminate It

This article explains the concept of false sharing in CPU caches, demonstrates its performance impact with Java code, analyzes the results, and shows how to prevent it using the @Contended annotation and appropriate JVM flags.

CPU cacheContended annotationJava performance
0 likes · 9 min read
How False Sharing Slows Java Programs and How to Eliminate It
Qunar Tech Salon
Qunar Tech Salon
Mar 23, 2015 · Fundamentals

Understanding CPU Cache: Purpose, Multi‑Level Design, Cache Lines, and Optimization Techniques

This article explains why CPU caches are needed, the evolution to multi‑level caches, the concept of cache lines, practical experiments demonstrating their impact, and how different cache organization strategies such as fully associative, direct‑mapped, and N‑way set‑associative affect performance and eviction policies.

CPU cachePerformance Optimizationcache architecture
0 likes · 14 min read
Understanding CPU Cache: Purpose, Multi‑Level Design, Cache Lines, and Optimization Techniques