This article explains the organization of main memory, covering memory slots, channels, controllers, DIMM modules, ranks, banks, burst mode, and the step‑by‑step process by which a memory request is serviced and a cache line is filled.
This article explains the concept of CPU cache false sharing, how it degrades performance on multi‑core systems, and provides practical techniques—including cache‑line alignment macros and padding strategies—to prevent it and improve multithreaded application efficiency.
This article explains the structure of modern CPU caches, the principles of cache lines, associativity, and coherence protocols, and demonstrates how these hardware details affect program performance through multiple code examples covering loop stride, matrix traversal, multithreading, and false sharing.
Baidu engineers boost C++ backend latency and cost efficiency by eliminating unnecessary string zero‑initialization, using zero‑copy split with SIMD, replacing deep protobuf merges with repeated string fields, employing job‑scoped arenas and custom memory resources for allocation, and applying prefetching, cache‑line awareness, and tuned memory‑order semantics, achieving multiplicative to order‑of‑magnitude speedups.
The article demonstrates how Top‑down Micro‑architecture Analysis Methodology (TMAM) can quickly pinpoint CPU bottlenecks—such as front‑end, back‑end, and bad speculation stalls—in a simple C++ accumulation loop, and shows that applying targeted compiler, alignment, and branch‑prediction optimizations reduces runtime by roughly 34 % while increasing retiring slots.
This article explains the concept of false sharing in CPU caches, demonstrates its performance impact with Java code, analyzes the results, and shows how to prevent it using the @Contended annotation and appropriate JVM flags.
False sharing occurs when multiple threads modify variables that reside on the same CPU cache line, causing unnecessary cache coherency traffic; this article explains cache line basics, CPU cache hierarchy, MESI protocol, and presents Java solutions—including padding, @sun.misc.Contended annotation, and JVM flags—to prevent performance degradation.
This article explains why CPU caches are needed, the evolution to multi‑level caches, the concept of cache lines, practical experiments demonstrating their impact, and how different cache organization strategies such as fully associative, direct‑mapped, and N‑way set‑associative affect performance and eviction policies.
