Architects' Tech Alliance
Mar 16, 2021 · Fundamentals
Power‑Saving Techniques for PCI Express IP in SoC Designs
This article explains three power‑saving techniques—clock gating, power gating, and protocol‑level power management—for PCI Express IP in system‑on‑chip designs, detailing their impact on dynamic and static power, implementation challenges, and how designers can achieve high energy efficiency while meeting fast recovery requirements.
Clock GatingPCI ExpressPower Management
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