This article explains the fundamentals of computer bus systems, details the architecture, transmission rates, and components of PCIe, and guides readers through PCIe device enumeration, BDF numbering, BAR addressing, and Linux sysfs interfaces for PCIe devices.
This article explains the PCIe architecture, the host's depth‑first enumeration process across buses, bridges and endpoints, demonstrates Linux lspci commands for inspecting devices, and details how PCIe memory accesses enable NVMe command submission and completion.
This article explains how a host discovers and configures PCIe devices through a depth‑first enumeration process, describes the BDF addressing scheme, and illustrates memory‑mapped I/O interactions such as NVMe command submission using Linux lspci commands.
This article explains the PCIe topology, the depth‑first enumeration algorithm used by x86 hosts to discover root complexes, switches and endpoints, shows Linux lspci commands for inspecting devices such as a Starblaze NVMe SSD, and details how PCIe memory space is used for command and data transfers.
This article explains how PCIe devices are discovered and accessed in an x86 system, detailing the hierarchical bus topology, depth‑first enumeration steps, configuration space handling, Linux lspci inspection, and NVMe command transmission through PCIe memory transactions.
