What Ten Lessons Google Learned from a Decade of TPU Evolution?

This article reviews a decade of Google TPU development, highlighting ten technical and architectural lessons, the hardware's impact on the AI industry, performance and energy‑efficiency improvements, and strategies for reducing machine‑learning carbon footprints.

Domain-specific ArchitectureGoogleMachine Learning Hardware

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What Ten Lessons Google Learned from a Decade of TPU Evolution?

Kuaishou Tech

Nov 8, 2021 · Artificial Intelligence

FPGA-Based Real-Time Streaming ASR Acceleration for Kuaishou: A Case Study in Domain-Specific Hardware Optimization

This paper presents a full fixed-point FPGA-based hardware acceleration solution for TDNN+LSTM acoustic models in real-time streaming ASR, achieving 37.67% latency reduction and 7.5x concurrency improvement through software-hardware co-design and domain-specific optimization.

Domain-specific ArchitectureFPGA accelerationTDNN+LSTM

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FPGA-Based Real-Time Streaming ASR Acceleration for Kuaishou: A Case Study in Domain-Specific Hardware Optimization

IT Architects Alliance

Jan 18, 2021 · Fundamentals

Post‑Moore’s Law CPU Performance: Laws, Domain‑Specific Architectures, and Optimization Strategies

In the post‑Moore’s‑law era, CPU performance gains have slowed, prompting a detailed analysis of three governing laws, the rise of domain‑specific architectures, and key optimization techniques such as reducing data movement, lowering precision, and increasing parallelism to guide future processor design.

CPU architectureDomain-specific ArchitectureMoore's Law

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Post‑Moore’s Law CPU Performance: Laws, Domain‑Specific Architectures, and Optimization Strategies