The Huawei Ascend 910 AI processor, built on the Da Vinci architecture with 7nm+ EUV technology, delivers 256 TFLOPS FP16 and 512 TOPS INT8 performance, superior energy efficiency, and a full-stack software ecosystem, making it ideal for large‑scale AI training, HPC, and cloud AI services.
This article details the design and evolution of DHPS, Kuaishou's load‑balanced, RDMA‑based high‑performance service architecture, explaining its network, storage, and traffic‑scheduling innovations that deliver over 270% query‑throughput improvement, lower latency, reduced CPU usage, and near‑five‑nine availability for large‑scale AI inference workloads.
The article reviews Fat‑Tree, Dragonfly, and Torus network topologies, analyzing their bandwidth, scalability, latency, routing algorithms, and cost trade‑offs for AI‑driven high‑performance computing clusters, and highlights each design's strengths and limitations in large‑scale deployments.
The article analyzes three major high‑performance‑computing network topologies—Fat‑Tree, Dragonfly, and Torus—detailing their design principles, scalability formulas, routing strategies, advantages, and limitations to help architects choose the most suitable architecture for large‑scale GPU clusters.
Renowned computer architect Gordon Bell, whose pioneering work on DEC’s PDP series, the creation of Bell’s Law, and leadership in supercomputing and high‑performance computing institutions, left an enduring legacy that continues to influence modern systems, AI, and the evolution of computing technology.
This article examines the evolution of network protocols from the OSI seven‑layer model and TCP/IP to RDMA technologies such as InfiniBand and RoCE, compares traditional three‑tier and leaf‑spine data‑center designs, and evaluates Ethernet, InfiniBand, and RoCE switches for high‑throughput, low‑latency HPC environments.
Dolphin VectorDB, created by Alibaba’s Alimama team, is a high‑performance, scalable vector database that delivers fast, cost‑effective AI‑driven vector storage and real‑time updates, supporting multiple query modes and powering applications such as content risk control, marketing Q&A, and audience selection, with ongoing enhancements for multimodal computing.
This article examines four leading exascale‑grade high‑performance processors—Fujitsu A64FX, NVIDIA H100, AMD MI250X, and Intel PonteVecchio—detailing their core architectures, compute resources, memory hierarchies, specialized accelerators, process technologies, performance metrics, and trends to inform future domestic processor development.
This article explains the concept and history of high‑performance computing (HPC), its serial and parallel processing architectures, performance metrics such as FLOPS, major application domains, and the rapid market growth and competitive landscape in China driven by national policies and industry investment.
This article explains the storage challenges of high‑performance computing—including traditional HPC, AI‑driven HPC, and HPDA—then details Baidu’s unified storage platform, object storage BOS, and runtime solutions PFS and RapidFS, illustrating their architecture, features, and a real‑world autonomous‑driving customer case.
The HiPChips workshop at ISCA 2022 gathered leading academia and industry experts to discuss the motivations, recent research breakthroughs, technical challenges, and ecosystem efforts surrounding high‑performance chiplet and interconnect architectures for future computing systems.
The talk details XtraPi’s journey from early PBS‑based supercomputers to a modern Kubernetes‑driven, multi‑cloud platform that uses Tencent Cloud TKE to run massive containerized drug‑discovery simulations, describing scaling strategies, image optimization, CI pipelines, checkpoint‑restart, and future serverless and bare‑metal enhancements.
