Tagged articles

memory ordering

5 articles · Page 1 of 1
Deepin Linux
Deepin Linux
Sep 26, 2024 · Fundamentals

Understanding CPU Cache Hierarchy, Write‑Back Strategy, and Memory Ordering in Multithreaded Programming

This article explains the structure and operation of modern CPU multi‑level caches, the write‑back caching policy, cache‑coherence mechanisms, atomic operations, and various memory‑ordering models in C++ multithreaded programs, providing detailed concepts, hardware and software solutions, and practical code examples.

C++Write-Backatomic-operations
0 likes · 32 min read
Understanding CPU Cache Hierarchy, Write‑Back Strategy, and Memory Ordering in Multithreaded Programming
Sohu Tech Products
Sohu Tech Products
Jun 2, 2021 · Fundamentals

Low‑Level Atomic Operations (SE‑0282) – Swift Atomics Overview

This article presents a comprehensive translation of the Swift Evolution proposal SE‑0282, detailing the design and implementation of low‑level atomic operations, memory orderings, and related types such as UnsafeAtomic and UnsafeAtomicLazyReference, providing examples and discussing integration with Swift’s concurrency model.

Swiftatomic-operationsconcurrency
0 likes · 57 min read
Low‑Level Atomic Operations (SE‑0282) – Swift Atomics Overview
Architects' Tech Alliance
Architects' Tech Alliance
Jan 3, 2021 · Backend Development

Code Migration Experience: Porting C/C++ Applications from x86 to TaiShan aarch64 Servers

This article presents a comprehensive guide on migrating business code from x86 to TaiShan aarch64 servers, covering language differences, compilation toolchains, architecture‑specific issues such as compiler options, assembly rewrites, memory ordering, floating‑point behavior, and recommended GCC optimizations.

AssemblyC#Code migration
0 likes · 14 min read
Code Migration Experience: Porting C/C++ Applications from x86 to TaiShan aarch64 Servers
Architects' Tech Alliance
Architects' Tech Alliance
Jan 21, 2020 · Backend Development

How to Seamlessly Migrate X86 C/C++ Code to Aarch64 TaiShan Servers

This guide details the migration of X86‑compiled C/C++ applications to Huawei TaiShan Aarch64 servers, covering language differences, required compiler versions, common build‑time errors, assembly rewrites, memory‑ordering quirks, floating‑point precision issues, and specific GCC flags to achieve correct and performant binaries.

Code migrationCompiler Flagsaarch64
0 likes · 14 min read
How to Seamlessly Migrate X86 C/C++ Code to Aarch64 TaiShan Servers