This article explains how Linux kernel Oops messages are generated, their format, the relationship between BUG, Oops and panic, and provides step‑by‑step debugging methods with code examples for ARM, PowerPC and MIPS architectures.
MIPS Tech has shifted from its legacy CPU architecture to RISC‑V, unveiling the high‑performance, scalable eVocore P8700 and power‑efficient I8500 multi‑processor IP cores aimed at high‑performance, real‑time applications such as networking, data centers, automotive, and edge computing.
The article outlines Wave Computing’s 2018 decision to open the MIPS Release 6 instruction set, describes the evolution and product lines of MIPS, compares the open‑source licensing and ecosystem of MIPS with RISC‑V, and discusses market adoption, commercial models, and future challenges.
This article provides a comprehensive technical review of the Chinese Loongson GS464E processor, covering its micro‑architectural design choices, instruction‑fetch and out‑of‑order execution units, cache hierarchy, benchmark results, manufacturing details, and the challenges it faces in competing with mainstream Intel and AMD CPUs.
Loongson, a leading Chinese chip maker, has announced it will drop all US‑origin technology and create a fully domestic instruction set called LoongArch—compatible with MIPS yet independent—while the article also details the complex history of MIPS licensing, US export restrictions, and the geopolitical pressures shaping China’s push for self‑reliant processor architectures.
This article explains the fundamental differences between CISC and RISC processor designs, outlines their respective advantages and drawbacks, and compares three major CPU architectures—x86, ARM, and MIPS—highlighting their histories, features, and typical application domains.
This article explains the fundamental differences between RISC and CISC architectures, reviews the historical development and technical characteristics of processors such as MIPS, ARM, and x86, and discusses why China’s Loongson chips favor the MIPS instruction set over alternatives.
The article provides a comprehensive overview of RISC principles and compares major processor families—including ARM, x86, Atom, MIPS, and PowerPC—detailing their architectures, performance characteristics, market adoption, and licensing models while also mentioning related DSP technologies and reference resources.
Wave Computing announced the open‑source release of the MIPS ISA and its R6 core in early 2019, positioning MIPS as a commercial‑ready alternative to RISC‑V while addressing ecosystem challenges, patent issues, and market dynamics in China and beyond.
This article explains the principles of Reduced Instruction Set Computing (RISC), compares its performance advantages over Complex Instruction Set Computing (CISC), and surveys major RISC families such as ARM, MIPS, PowerPC, as well as Intel's low‑power Atom line and their roles in modern devices.
Wave Computing announced that the MIPS instruction set architecture and its latest R6 core will be released as open source in early 2019, sparking industry debate about the move’s impact on MIPS’s market position, licensing revenue, and competition with RISC‑V, especially in the AI and Chinese markets.
