This article deeply dissects the hardware origins of SMP multi‑core out‑of‑order execution, explains four classic memory‑reordering scenarios, and shows how Linux kernel memory barriers constrain the chaos, enabling developers to reliably reason about and fix complex multi‑core concurrency bugs.
Exploring the historical shift from memory‑constrained SMP systems and POSIX threads to today’s powerful hardware, this article argues that the ‘share‑nothing’ concurrency principle—embodied in Go’s CSP model and PHP’s parallel extension—should replace legacy lock‑based paradigms as the default approach.
This article explains how Linux memory barriers work, why they are needed on SMP systems, the different barrier types, their kernel implementations, and practical examples showing their impact on multithreaded performance and driver development.
This article explains the three main commercial server architectures—SMP, NUMA, and MPP—detailing their structures, performance characteristics, scalability limits, and suitability for OLTP versus data‑warehouse workloads, while also covering practical considerations such as virtualization and real‑world examples.
This article outlines the main server hardware architectures—SMP, UMA, and NUMA—explains shared-storage models, details multi-core cache structures from private L1 to shared L3, compares access latencies, and discusses inter-core communication mechanisms and cache coherency protocols.
Tencent’s iData analysis center selected Spark as its new computing platform because, unlike ElasticSearch, TiDB, and other MPP solutions, Spark offers iterative processing, shuffle support, robust SQL and DAG scheduling, and flexible SMP‑style data exchange, enabling efficient OLAP on billions of game‑user records.
This article explains the concepts of MPI, OpenMPI, and OpenMP, compares three major server architectures—SMP, NUMA, and MPP—and discusses their performance characteristics, scalability limits, and typical application scenarios in high‑performance computing.
This article explains Linux interrupt handling mechanisms, covering the basic vector‑table approach, the need for bottom‑half processing, and the three main techniques—softirqs, tasklets, and workqueues—while highlighting their advantages, SMP support, and proper usage guidelines.
This guide explains what hardware interrupts are, how SMP IRQ affinity works, and provides step‑by‑step Linux commands to assign specific device IRQs—such as network or disk—to individual CPU cores, improving multi‑core server performance and throughput.
This article explains why high CPU usage on Linux servers isn’t always a problem, describes how to identify true CPU bottlenecks using tools like uptime, top, sar and vmstat, and offers practical tuning steps such as stopping unnecessary processes, adjusting priorities, using CPU affinity, and updating drivers.
