Decoding Huawei’s τ (Tau) Law: Why Time‑Scaling May Replace Moore’s Geometry

The article examines Huawei’s newly announced τ (Tau) Law, which proposes scaling semiconductor performance by reducing signal‑propagation delay rather than shrinking transistor geometry, explains its RC‑delay model, logical‑folding technique, multi‑layer optimization framework, and compares it with existing 3D‑stacking approaches, while assessing its practical challenges and industry implications.

RC delaySTCOchip design

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Decoding Huawei’s τ (Tau) Law: Why Time‑Scaling May Replace Moore’s Geometry

Java Tech Enthusiast

May 29, 2026 · Industry Insights

What Is Huawei’s New “τ (Tau) Law” and How Does It Challenge Moore’s Law?

Huawei introduced the “τ (Tau) Law” at ISCAS 2026, proposing a shift from geometric scaling to time‑constant reduction to overcome the physical limits of Moore’s Law, and outlines how signal‑propagation delay can be compressed through system‑level innovations such as logical folding and advanced packaging.

HuaweiMoore's LawSignal Propagation

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What Is Huawei’s New “τ (Tau) Law” and How Does It Challenge Moore’s Law?

AI Large-Model Wave and Transformation Guide

May 25, 2026 · Industry Insights

When Moore’s Law Hits the Wall, China Takes a New Chip Road with Huawei’s “Tau Law”

Huawei’s He Tingbo announced at ISCAS 2026 that Moore’s geometric scaling has reached a physical ceiling and introduced the “Tau Law,” a time‑scaling strategy that leverages multi‑layer optimization, logic folding, and the Lingqu bus to achieve 1.4 nm‑equivalent performance without EUV, outlining a roadmap to 2026 and 2031.

EUVHuaweiMoore's Law

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When Moore’s Law Hits the Wall, China Takes a New Chip Road with Huawei’s “Tau Law”