Forgotten Ternary Logic vs τ Law: Why Huawei’s “Bottom‑Layer Revolution” Sparks Controversy
The article analyzes Huawei’s ternary‑logic chip and the τ (tau) law, tracing their historical roots, technical claims, patent details, performance numbers, ecosystem challenges, market reactions, and the intense industry debate over whether they represent genuine breakthroughs or elaborate marketing narratives.
1. Huawei Ternary Logic: Origin and Claims
1.1 Revival of the Soviet Setun
Huawei’s ternary‑logic concept traces back to the 1958 Soviet Setun computer, which used balanced ternary states (‑1, 0, +1). The Setun was praised for lower cost, higher efficiency, and lower fault rates compared with contemporary binary machines, but it failed to scale due to hardware instability, a binary‑centric ecosystem, and policy cancellation.
1.2 Patent and Claimed Benefits
On 18 September 2023 Huawei filed patent CN119652311A for “ternary logic gates, computing circuits, chips and electronic devices,” published on 18 March 2025. The patent claims that ternary logic can reduce transistor count by ~40 % and cut power consumption to one‑third of traditional binary gates. Information entropy rises to 1.585 bits/symbol, enabling more data per chip area. Huawei laboratory data reports a 47 % speed increase for AI training workloads while keeping chip temperature below 40 °C.
1.3 Not the Sole Pioneer
In July 2019, UNIST (Korea) demonstrated a large‑wafer ternary metal‑oxide semiconductor using a 0‑1‑2 ternary system, published in Nature Electronics . Samsung later verified the approach. Huawei’s distinction is the first commercial‑grade integration of ternary logic gates, computing circuits, and chip packaging.
1.4 Implementation Hurdles
Physical challenges include precise voltage control for three distinct levels, which dramatically raises manufacturing tolerances. Yield estimates for a 7 nm ternary chip are ~78 % versus 92 % for binary, implying nearly double waste. The ecosystem barrier is even larger: a complete rewrite of instruction sets, compilers, programming languages, data standards, and network protocols would be required, a transformation analysts say would take at least a decade and $20 billion.
1.5 Industry View
Analyst “E. T. Jensen” examined the patent and highlighted the novelty of a 7‑transistor ternary gate but warned that commercial CPUs remain far off and that the patent’s primary value is a claim of technical sovereignty rather than immediate revenue.
2. τ Law: Huawei’s Second “Bottom‑Layer Revolution”
2.1 Announcement
On 25 May 2026 at ISCAS 2026 in Shanghai, Huawei Semiconductor President He Tingbo introduced the τ (tau) law, describing “time‑scaling” (logic folding) as a new guiding principle that compresses signal propagation delay to increase transistor density without relying on EUV lithography.
2.2 Market Reaction
The news triggered a sharp rally in China’s semiconductor stocks; SMIC hit its daily limit with a ¥370 billion turnover, while Hua Hong and Dongxin saw 20 % limit‑up moves. Omdia analyst He Hui interpreted the surge as market confidence in a domestic path to bypass EUV constraints. Brokerage reports (e.g., AiJian Securities, Dongxing Securities) described τ law’s logic‑folding as vertical stacking and ultra‑fine hybrid bonding that can improve frequency and energy efficiency.
2.3 Criticism
TSMC senior VP Zhang Xiaoqiang stated the concept has existed for years, mainly as tighter 3D integration. Nvidia CEO Jensen Huang acknowledged the technique’s engineering merit but argued that TSMC has been using similar 3D‑stacking and CoWoS technologies for a decade, so the claim is not a threat. EETimes published a “demystifying” article labeling τ law as repackaged industry‑wide practices wrapped in marketing rhetoric.
2.4 “Equivalent 1.4 nm” Debate
He Tingbo’s 2031 target of “equivalent to a 1.4 nm process” refers to achieving comparable transistor density through logic folding and system‑level optimization, not a physical 1.4 nm node. Critics note the lack of a clear conversion methodology and question how the claim stacks against TSMC’s definition of 1.4 nm performance.
3. Comparative Analysis of Ternary Logic and τ Law
3.1 Shared Narrative Pattern
Both concepts follow a similar story arc: (1) declare the end of an old binary or Moore’s‑law paradigm, (2) present a novel solution (ternary or time‑scaling), (3) hype a revolutionary impact, and (4) forecast China defining future chip standards.
3.2 Technical Differences
Ternary logic rewrites the fundamental representation of data at the transistor level—a “engine replacement.” τ law optimizes system‑level design, such as logic folding and advanced packaging—a “vehicle‑level” improvement. Consequently, ternary faces exponential ecosystem reconstruction, while τ law confronts logarithmic challenges limited to manufacturing and integration.
3.3 Historical Risk
The 1960s Soviet ternary computer failure illustrates that disruptive hardware requires a coordinated industry shift, not a single company’s effort. For ternary, the required global software and hardware overhaul makes short‑term commercialization unlikely. τ law, being an engineering refinement of existing 3D‑stacking and chiplet techniques, faces a lower barrier but risks losing narrative momentum if the industry perceives it merely as rebranding.
4. Conclusion: Technical Revolution or Marketing Narrative?
Huawei’s ternary‑logic research represents a solid theoretical advance but is hampered by massive ecosystem and yield obstacles, likely confining it to patents and laboratory prototypes for the foreseeable future. τ law offers a pragmatic engineering pathway that aligns with global trends in advanced packaging, yet its “revolutionary” label is overstated. Both initiatives serve Huawei’s broader strategic aim of shaping a domestic discourse that positions China as a rule‑definer in semiconductor technology.
References
[1] EET China: “华为重拾三进制,为什么?” https://www.eet-china.com/mp/a394616.html
[2] EET China: “三进制涅槃重生!华为公布三进制逻辑门专利!” https://www.eet-china.com/mp/a393650.html
[3] EET China: “祛魅韬定律 舆论造神贪天之功” https://www.eet-china.com/mp/a498832.html
[4] EET China: “华为韬定律刷屏!台积电说概念早有、黄仁勋称领先十年,真相来了” https://www.eet-china.com/mp/a498929.html
[5] OFweek电子工程网: “重磅!华为公布新芯片技术!” https://ee.ofweek.com/2025-04/ART-8140-2801-30660656.html
[6] 太平洋科技快讯: “华为申请三进制逻辑门电路相关专利” https://g.pconline.com.cn/x/1912/19122832.html
[7] 网易科学: “三进制芯片,会是一场降维打击吗?” https://www.163.com/dy/article/K2JV8FEH0532C74T.html
[8] 网易科技: “华为搞了个三进制芯片,能颠覆现在的电脑手机吗?” https://www.163.com/dy/article/JS3QOHFO05168SG2.html
[9] 搜狐科技: “华为押注三进制芯片:绕开极紫外光刻机,真能实现弯道超车?” https://m.sohu.com/a/1019335670_122574932
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DeepNoMind
I’m Yu Fan, a tech leader with deep technical expertise and managerial vision. Formerly at Motorola, now at Mavenir, I’ve led teams for years, focusing on backend architecture and cloud-native solutions, staying abreast of AI and other frontier fields, and championing personal growth and lifelong learning.
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