How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

At ISCAS 2026, Huawei’s He Tingbo unveiled the “τ Law,” a time‑scaling theory that replaces geometric miniaturization with LogicFolding to cut signal‑travel time, delivering up to 55% higher transistor density, 41% better SoC efficiency, and a portfolio of 381 chips over six years.

HuaweiISCAS2026chip design

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How Huawei’s “τ Law” Redefines Chip Scaling by Shrinking Time, Not Geometry

IT Services Circle

May 26, 2026 · Industry Insights

What Is Huawei’s New “τ (Tau) Law” for Semiconductors?

Huawei introduced the “τ (Tau) Law” at the 2026 ISC conference, proposing a shift from geometric scaling of Moore’s law to “time miniaturization” that reduces signal propagation delay through logical folding and interconnect redesign, aiming to sustain semiconductor performance as transistor sizes near physical limits.

HuaweiMoore's Lawchip design

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What Is Huawei’s New “τ (Tau) Law” for Semiconductors?